Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 20180301551 A1), in view of Migita (US 20160308019 A1), Strassburg (US 20110012088 A1), Ma (US 20190356114 A1), and Chu-Kung (US 20200266296 A1).
Regarding independent claim 1, Majhi teaches a tunneling current driven element ([0020], "Described herein are heterojunction TFETs incorporating one or more semiconducting oxide."), comprising: a first conductivity type semiconductor layer formed of an indirect transition semiconductor material, the first conductivity type semiconductor layer having a first conductivity type which is a conductivity type of at least one selected from the group consisting of a "p" type and an "n" type (Fig. 1A, 130; [0026], "Referring back to FIG. 1, in some embodiments, one or more of p-type material 130, channel material 140, and n-type material 150 is a non-oxide semiconductor, such as, but not limited to, an elemental or alloyed group IV (IUPAC group 14) semiconductor (e.g., Si, Ge, or SiGe, GeSn, etc.)...", (According to the present application, indirect transition semiconductor materials include group IV semiconductors)), a second conductivity type semiconductor layer formed of the indirect transition semiconductor material, the second conductivity type semiconductor layer having a second conductivity type which is a conductivity type different from the first conductivity type (Fig. 1A, 150; [0026], "Referring back to FIG. 1, in some embodiments, one or more of p-type material 130, channel material 140, and n-type material 150 is a non-oxide semiconductor, such as, but not limited to, an elemental or alloyed group IV (IUPAC group 14) semiconductor (e.g., Si, Ge, or SiGe, GeSn, etc.)...", (According to the present application, indirect transition semiconductor materials include group IV semiconductors)); and an intermediate layer arranged so as to be sandwiched between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer (Fig. 1A, 140; [0026], "Referring back to FIG. 1, in some embodiments, one or more of p-type material 130, channel material 140, and n-type material 150 is a non-oxide semiconductor, such as, but not limited to, an elemental or alloyed group IV (IUPAC group 14) semiconductor (e.g., Si, Ge, or SiGe, GeSn, etc.)..."), the intermediate layer being formed of at least one selected from the group consisting of an intrinsic semiconductor and an impurity-containing semiconductor having an impurity concentration lower than impurity concentrations of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer ([0024], "...in which case n-type material 150 may differ in composition from channel material 140 only with respect to a higher electrically-active impurity concentration.").
However, Majhi does not teach the first conductivity type semiconductor layer…having an impurity concentration of 3x10^19 cm-3 or more; and wherein the intermediate layer is a layer having a laminate structure in which, assuming a first direction directed from the first conductivity type semiconductor layer toward the second conductivity type semiconductor layer as a laminating direction, on the first conductivity type semiconductor layer serving as a base layer, at least one first base material layer and at least one quantum well layer are alternately laminated in the stated order, and a second base material layer is laminated on the at least one quantum well layer on a side closest to the second conductivity type semiconductor layer, wherein the at least one first base material layer is a layer that is formed of a first semiconductor material selected from the indirect transition semiconductor material and has a thickness in the first direction of from 0.5 nm to 20 nm, wherein the second base material layer is a layer that is formed of a second semiconductor material selected from the indirect transition semiconductor material and has a thickness in the first direction of from 10 nm to 500 nm, and wherein the at least one quantum well layer is a layer that is formed of a third semiconductor material selected from the indirect transition semiconductor material of a type different from the first semiconductor material and the second semiconductor material and has a thickness in the first direction of from 0.5 nm to 10 nm, the third semiconductor material being selected from the indirect transition semiconductor material having a band structure of at least one selected from the group consisting of a first band structure and a second band structure, the first band structure having a valence band edge present at an energy position higher than valence band edges of the first semiconductor material and the second semiconductor material, the second band structure having a conduction band edge present at an energy position lower than conduction band edges of the first semiconductor material and the second semiconductor material.
However, in the same field of endeavor, Migita teaches the first conductivity type semiconductor layer…having an impurity concentration of 3x10^19 cm-3 or more ([0088], "An impurity introduced into the source region 23 and the drain region 24 by ion implantation was As, and the impurity concentration was 1×10^20/cm^3."); Strassburg teaches wherein the intermediate layer is a layer having a laminate structure in which, assuming a first direction directed from the first conductivity type semiconductor layer toward the second conductivity type semiconductor layer as a laminating direction, on the first conductivity type semiconductor layer serving as a base layer, at least one first base material layer and at least one quantum well layer are alternately laminated in the stated order, and a second base material layer is laminated on the at least one quantum well layer on a side closest to the second conductivity type semiconductor layer (Fig. 3, 23a, 23b, 23c; [0069], "The intermediate layer 23 is provided with the imperfections 6 in a central region 23b, while the region 23a that adjoins or is adjacent to the n-type tunnel junction layer 21 and also the region 23c of the intermediate layer 23 that adjoins or is adjacent to the p-type tunnel junction layer 22 are not provided with the imperfections 6 in a targeted manner, that is to say, in particular, are free of the imperfections 6."), Ma teaches wherein the at least one first base material layer is a layer that is formed of a first semiconductor material selected from the indirect transition semiconductor material and has a thickness in the first direction of from 0.5 nm to 20 nm (Fig. 1A, 107; [0022], "Next, another layer of amorphous inorganic material is deposited as a second quantum barrier layer 107 (panel b5).", [0031], "For many device applications, the layer thicknesses of the quantum barrier layers and the quantum well layers will be in the range from about 2 nm to about 100 nm, including in the range from about 2 nm to about 50 nm, and further including in the range from about 3 nm to about 20 nm.", (Amorphous silicon is an amorphous inorganic material and also a group IV semiconductor, meaning it is an indirect transition semiconductor)), wherein the second base material layer is a layer that is formed of a second semiconductor material selected from the indirect transition semiconductor material and has a thickness in the first direction of from 10 nm to 500 nm (Fig. 1A, 107'; [0022], "he transfer printing and inorganic layer deposition steps can be repeated multiple times to build up a superlattice structure having the desired number of quantum wells (103′) and barriers (107′) (panels c1 and c2).", [0031], "For many device applications, the layer thicknesses of the quantum barrier layers and the quantum well layers will be in the range from about 2 nm to about 100 nm, including in the range from about 2 nm to about 50 nm, and further including in the range from about 3 nm to about 20 nm.", (Amorphous silicon is an amorphous inorganic material and also a group IV semiconductor, meaning it is an indirect transition semiconductor)), and wherein the at least one quantum well layer is a layer that is formed of a third semiconductor material selected from the indirect transition semiconductor material of a type different from the first semiconductor material and the second semiconductor material and has a thickness in the first direction of from 0.5 nm to 10 nm (Fig. 1A, 103'; [0026], "Examples of semiconductor materials that can be used as the quantum wells and coupled with the above-referenced inorganic materials in a superlattice include Group IV semiconductors, such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe).", [0031], "For many device applications, the layer thicknesses of the quantum barrier layers and the quantum well layers will be in the range from about 2 nm to about 100 nm, including in the range from about 2 nm to about 50 nm, and further including in the range from about 3 nm to about 20 nm."), and Chu-Kung teaches the third semiconductor material being selected from the indirect transition semiconductor material having a band structure of at least one selected from the group consisting of a first band structure and a second band structure, the first band structure having a valence band edge present at an energy position higher than valence band edges of the first semiconductor material and the second semiconductor material (Fig. 4b), the second band structure having a conduction band edge present at an energy position lower than conduction band edges of the first semiconductor material and the second semiconductor material (Fig. 4a).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element of Majhi with the concentration of Migita "in order to suppress a parasitic resistance", (Migita, [0050]), the intermediate layer structure of Strassburg so that "improved electronic properties of the tunnel junction can be obtained", (Strassburg, [0023]), the materials and thicknesses of Ma so as to "to confine excitons (electrons and holes), as well as to avoid unwanted recombination sites", (Ma, [0002]), and the band structures of Chu-Kung so that "the extrinsic resistance of the device remains low", (Chu-Kung, [0017]).
Regarding dependent claim 2, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 1. However, as previously combined, they do not teach wherein the band structure is at least one selected from the group consisting of a first band structure and a second band structure, the first band structure having the valence band edge present at an energy position higher by more than 0.1 eV than a valence band edge having a highest energy position out of the first semiconductor material and the second semiconductor material, the second band structure having the conduction band edge present at an energy position lower by more than 0.1 eV than a conduction band edge having a lowest energy position out of the first semiconductor material and the second semiconductor material.
However, Chu-Kung further teaches wherein the band structure is at least one selected from the group consisting of a first band structure and a second band structure, the first band structure having the valence band edge present at an energy position higher by more than 0.1 eV than a valence band edge having a highest energy position out of the first semiconductor material and the second semiconductor material (Fig. 4b; [0083], "...wherein the second semiconductor material provides a valence band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material…"), the second band structure having the conduction band edge present at an energy position lower by more than 0.1 eV than a conduction band edge having a lowest energy position out of the first semiconductor material and the second semiconductor material (Fig. 4a; [0110], "...wherein the second semiconductor material provides a conduction band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element as described by the combination of Majhi, Migita, Strassburg, Ma, and Chu-Kung with the band edges of Chu-Kung so that "the extrinsic resistance of the device remains low", (Chu-Kung, [0017]).
Regarding dependent claim 5, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 1. However, as previously combined, they do not teach wherein the first conductivity type semiconductor layer, the second conductivity type semiconductor layer and the intermediate layer are each formed as a single crystal layer of the indirect transition semiconductor material.
However, Ma further teaches wherein the first conductivity type semiconductor layer, the second conductivity type semiconductor layer and the intermediate layer are each formed as a single crystal layer of the indirect transition semiconductor material ([0023], "For example, a n-type contact layer 108, which may be a transferred single-crystalline semiconductor nanomembrane…", [0015], "Superlattice structures composed of single-crystal semiconductor wells and amorphous barriers are provided.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element as described by the combination of Majhi, Migita, Strassburg, Ma, and Chu-Kung with the single crystal layers of Ma so that the layers "are thin enough to allow carrier transport and tunneling to take place", (Ma, [0016]).
Regarding dependent claim 6, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 1. However, as previously combined, they do not teach wherein the thickness of the at least one first base material layer in the first direction is 8 nm or less.
However, Strassburg further teaches wherein the thickness of the at least one first base material layer in the first direction is 8 nm or less (Fig. 3, 231, 233; [0058], "The n-barrier layer 231 and the p-barrier layer 233 have, for example, a layer thickness of less than or equal to 1 nm.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element as described by the combination of Majhi, Migita, Strassburg, Ma, and Chu-Kung with the thickness of the base material layer of Strassburg so that "a particularly high charge carrier density can be brought about", (Strassburg, [0025]).
Regarding dependent claim 8, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 1, and further teaches further comprising an element structure of a tunneling field effect transistor in which a channel region is formed between a source region and a drain region (Fig. 1A, 130, 140, 150; [0021], "Returning to FIG. 1A, hTFET 101 includes a channel material 140 separating a p-type material 130 having p-type conductivity from an n-type material 150 having n-type conductivity."), and a gate electrode is formed above the channel region through intermediation of a gate insulating film (Fig. 1A, 173, 171; [0021], "A gate dielectric material 171 separates a gate electrode material 173 from channel material 140."), wherein the source region is formed of the first conductivity type semiconductor layer (Fig. 1A, 130; [0021], "...p-type material 130 functions as a source…"), the drain region is formed of the second conductivity type semiconductor layer (Fig. 1A, 150; [0024], "...drain n-type material 150 may form a second heterojunction with channel material 140. "), and the channel region is formed of the intermediate layer (Fig. 1A, 140; [0021], "Returning to FIG. 1A, hTFET 101 includes a channel material 140…").
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 20180301551 A1), in view of Migita (US 20160308019 A1), Strassburg (US 20110012088 A1), Ma (US 20190356114 A1), Chu-Kung (US 20200266296 A1), Iesaka (US 20210343882 A1), Curatola (US 20090289298 A1), Jin (US 20080237575 A1), and Chen (US 20230395504 A1).
Regarding dependent claim 3, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 1, and further teaches wherein the first semiconductor material, the second semiconductor material and the third semiconductor material are at least one selected from the group consisting of the following combinations (1) to (6): (2) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Ge ([0026], "Referring back to FIG. 1, in some embodiments, one or more of p-type material 130, channel material 140, and n-type material 150 is a non-oxide semiconductor, such as, but not limited to, an elemental or alloyed group IV (IUPAC group 14) semiconductor (e.g., Si, Ge, or SiGe, GeSn, etc.)...").
However, as previously combined, they do not teach (1) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Si1-xGex, where "x" exceeds 0 and is less than 1; (3) a combination in which the first semiconductor material and the second semiconductor material are Si1-xGex, where "x" exceeds 0 and is less than 1, and the third semiconductor material is Si1-yGey, where "y" is a value exceeding 0 and being less than 1 and further being larger than "x"; (4) a combination in which the first semiconductor material and the second semiconductor material are Si1-xGex, where "x" exceeds 0 and is less than 1, and the third semiconductor material is Ge; (5) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Si1-xCx, where "x" exceeds 0 and is less than 1; and (6) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Si1-x-yGexCy, where "x" exceeds 0 and is less than 1, "y" exceeds 0 and is less than 1, and "x+y" is less than 1.
However, in the same field of endeavor, Iesaka teaches (1) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Si1-xGex, where "x" exceeds 0 and is less than 1 ([0059], "The epitaxial layers of silicon layer 82, Si1-xGex layer 84 and silicon layer 86 is formed on the semiconductor substrate 80, for example by epitaxial growth...where in x can range between 0 and 1."); Curatola teaches (3) a combination in which the first semiconductor material and the second semiconductor material are Si1-xGex, where "x" exceeds 0 and is less than 1, and the third semiconductor material is Si1-yGey, where "y" is a value exceeding 0 and being less than 1 and further being larger than "x" (Fig. 10a, 102, 103, 104; [0079], "The Si.sub.1-xGex layer 102 (where the ratio x is different to the ratio y for the second layer 103)…"); Jin teaches (4) a combination in which the first semiconductor material and the second semiconductor material are Si1-xGex, where "x" exceeds 0 and is less than 1, and the third semiconductor material is Ge ([0023], "...due to the faceted growth of Si1-xGex on the sidewalls of the Si fin 111 of FIG. 2, preferential oxidation may completely convert the bottom boundary of the Si fin 111 to SiO2, such that the Ge/Si1-yGey nanowire core…"); and Chen teaches (5) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Si1-xCx, where "x" exceeds 0 and is less than 1 ([0033], "The crystalline semiconductor material may be elemental (e.g., Si, or Ge, or the like), or an alloy (e.g., Si1-xCx, or Si1-xGex, Si1-x-yGexCy, or the like).", [0027], "The semiconductor of the active layer and the bulk semiconductor generally comprise the crystalline semiconductor material silicon..."); and (6) a combination in which the first semiconductor material and the second semiconductor material are Si and the third semiconductor material is Si1-x-yGexCy, where "x" exceeds 0 and is less than 1, "y" exceeds 0 and is less than 1, and "x+y" is less than 1 ([0033], "The crystalline semiconductor material may be elemental (e.g., Si, or Ge, or the like), or an alloy (e.g., Si1-xCx, or Si1-xGex, Si1-x-yGexCy, or the like).", [0027], "The semiconductor of the active layer and the bulk semiconductor generally comprise the crystalline semiconductor material silicon...").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element as described by the combination of Majhi, Migita, Strassburg, Ma, and Chu-Kung with the combination of Iesaka so that "charges can be transferred easily and completely", (Iesaka, [0034]), the combination of Curatola so that "the intrinsic 60 mV/decade limit can be overcome", (Curatola, [0005]), the combination of Jin so as to have "an increased device speed", (Jin, [0002]), and the combinations of Chen for "increasing production efficiency and lowering associated costs", (Chen, [0001]).
Regarding dependent claim 4, Majhi, as previously modified by Migita, Strassburg, Ma, Chu-Kung, Iesaka, Curatola, Jin, and Chen, teaches the tunneling current driven element according to claim 3. Iesaka further teaches wherein the first semiconductor material, the second semiconductor material and the third semiconductor material are the combination (1), and "x" is 0.12 or more ([0040], "The ratio x of Ge starts at zero or close to zero (i.e., the SiGe layer having very low or zero Ge concentration) at the first face 321 of the charge generation region 32a in the Si layer 82, and increases to about 0.7 at a certain depth into the Si1-xGex layer 84 (e.g., at about 2 μm).").
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 20180301551 A1), in view of Migita (US 20160308019 A1), Strassburg (US 20110012088 A1), Ma (US 20190356114 A1), Chu-Kung (US 20200266296 A1), and Berger (US 20030049894 A1).
Regarding dependent claim 7, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 1. However, as previously combined, they do not teach further comprising an element structure of a tunneling diode in which, between an n-type semiconductor layer and a p-type semiconductor layer, a low impurity concentration layer is arranged, the low impurity concentration layer being formed of at least one selected from the group consisting of an intrinsic semiconductor and an impurity-containing semiconductor having an impurity concentration lower than impurity concentrations of the n-type semiconductor layer and the p-type semiconductor layer, wherein the element structure includes at least one selected from the group consisting of a first element structure and a second element structure, the first element structure including: the n- type semiconductor layer formed of a first conductivity type semiconductor layer having a first conductivity type being an "n" type; the p-type semiconductor layer formed of a second conductivity type semiconductor layer having a second conductivity type being a "p" type; and the low impurity concentration layer formed of an intermediate layer, the second element structure including: the p-type semiconductor layer formed of the first conductivity type semiconductor layer having the first conductivity type being the "p" type; the n-type semiconductor layer formed of the second conductivity type semiconductor layer having the second conductivity type being the "n" type; and the low impurity concentration layer formed of the intermediate layer.
However, in the same field of endeavor, Berger teaches further comprising an element structure of a tunneling diode in which, between an n-type semiconductor layer and a p-type semiconductor layer, a low impurity concentration layer is arranged (Fig. 3, 50, 80, 55, 65; [0076], "Injector layers 50 and 80...may be doped in the range of 1x10^10/cm^3 to 1x10^22/cm^3, or more preferably in the range of 1x10^18/cm^3 to 5x10^19/cm^3, 1x10^15/cm^3 to 5x10^21/cm^3, or 1x10^17/cm^3 to 5x10^21/cm^3.", [0077], "With respect to quantum well layers 55 and 75...typical sheet carrier concentrations are on the order of 1x10^12 cm^-2 to 1x10^15 cm^-2.", (As can be seen, the middle well layers are lightly doped compared to the outer ones)), the low impurity concentration layer being formed of at least one selected from the group consisting of an intrinsic semiconductor and an impurity-containing semiconductor having an impurity concentration lower than impurity concentrations of the n-type semiconductor layer and the p-type semiconductor layer ([0068], "Such layers may include but are not limited to the following: Si, Ge, C, Sn, Si1-xGex, Si1-xCx, Si1-xSnx, Si1-x-yGexCy, Si1-x-y-zGexCySnz, Si1-xNx, Al1-xOx…"), wherein the element structure includes at least one selected from the group consisting of a first element structure and a second element structure, the first element structure including: the n- type semiconductor layer formed of a first conductivity type semiconductor layer having a first conductivity type being an "n" type; the p-type semiconductor layer formed of a second conductivity type semiconductor layer having a second conductivity type being a "p" type ([0068], "That is, the "top" may refer to an n-type material concurrent with "bottom" referring to a p-type material, or alternatively "top" may refer to a p-type layer concurrent with "bottom" referring to an n-type layer."); and the low impurity concentration layer formed of an intermediate layer (Fig. 3, 50, 80, 55, 65; [0076], "Injector layers 50 and 80...may be doped in the range of 1x10^10/cm^3 to 1x10^22/cm^3, or more preferably in the range of 1x10^18/cm^3 to 5x10^19/cm^3, 1x10^15/cm^3 to 5x10^21/cm^3, or 1x10^17/cm^3 to 5x10^21/cm^3.", [0077], "With respect to quantum well layers 55 and 75...typical sheet carrier concentrations are on the order of 1x10^12 cm^-2 to 1x10^15 cm^-2.", (As can be seen, the middle well layers are lightly doped compared to the outer ones)), the second element structure including: the p-type semiconductor layer formed of the first conductivity type semiconductor layer having the first conductivity type being the "p" type; the n-type semiconductor layer formed of the second conductivity type semiconductor layer having the second conductivity type being the "n" type ([0068], "That is, the "top" may refer to an n-type material concurrent with "bottom" referring to a p-type material, or alternatively "top" may refer to a p-type layer concurrent with "bottom" referring to an n-type layer."); and the low impurity concentration layer formed of the intermediate layer (Fig. 3, 50, 80, 55, 65; [0076], "Injector layers 50 and 80...may be doped in the range of 1x10^10/cm^3 to 1x10^22/cm^3, or more preferably in the range of 1x10^18/cm^3 to 5x10^19/cm^3, 1x10^15/cm^3 to 5x10^21/cm^3, or 1x10^17/cm^3 to 5x10^21/cm^3.", [0077], "With respect to quantum well layers 55 and 75...typical sheet carrier concentrations are on the order of 1x10^12 cm^-2 to 1x10^15 cm^-2.", (As can be seen, the middle well layers are lightly doped compared to the outer ones)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element as described by the combination of Majhi, Migita, Strassburg, Ma, and Chu-Kung with the diode structure of Berger for "reducing the number of components per circuit function, increasing speed, and lowering power consumption", (Berger, [0005]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 20180301551 A1), in view of Migita (US 20160308019 A1), Strassburg (US 20110012088 A1), Ma (US 20190356114 A1), Chu-Kung (US 20200266296 A1), and Kuramochi (US 20210231867 A1).
Regarding dependent claim 9, Majhi, as previously modified by Migita, Strassburg, Ma, and Chu-Kung, teaches the tunneling current driven element according to claim 8. However, as previously combined, they do not teach wherein a length of the at least one quantum well layer in a second direction orthogonal to the first direction as viewed from a position in contact with the gate insulating film is at least 5 nm.
However, in the same field of endeavor, Kuramochi teaches wherein a length of the at least one quantum well layer in a second direction orthogonal to the first direction as viewed from a position in contact with the gate insulating film is at least 5 nm ([0041], "The active medium 105, which has a multiple quantum well structure, has a length of 950 nm in the direction of the resonator and a width of 300 nm.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the tunneling current driven element as described by the combination of Majhi, Migita, Strassburg, Ma, and Chu-Kung with the quantum well layer length of Kuramochi for "increasing the efficiency", (Kuramochi, [0018]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20180331255 A1, pertaining to a device with a tunnel junciton.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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