DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 19 and 20 recites the limitation "the enable delay switch" in claim 19. There is insufficient antecedent basis for this limitation in the claim. Examiner will conclude for continual prosecution that the enable delay switch portion is removed to put the independent claim 19 to be similar to the other independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-10, and 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa (Pub 2013/0176082) in view of Kucharewski (Patent 3973222).
As to claim 1, Ishikawa teaches an oscillator circuit(fig 4) comprising: a first inverter (IV1) that is electrically connected to a supply voltage (VDD, paragraphs 23 and 36), a first node (connected to C2, C1, R0), and a second node (N1);
a second inverter (IV2) that is electrically connected to the supply voltage (VDD), the second node, and a third node N2);
a third inverter (IV3) that is electrically connected to the supply voltage (VDD), the third node N2), and a fourth node (N3);
a resistor (R0) that is electrically connected to the fourth node;
a first capacitor (C1) that is electrically connected to the third node (N2) and a sixth node that is electrically connected to the fifth node;
and a second capacitor (C2) that is electrically connected to the sixth node and a ground (Vss), wherein the first capacitor and the second capacitor form a capacitor divider (C1 and C2 form a divider), and wherein the capacitor divider limits a first voltage at the first node to a voltage range between the supply voltage and the ground (paragraphs 24, 25, and 36).
Ishikawa does not teach an enable transistors connected to the supply voltage and fifth node.
Kucharewski teaches an RC oscillator (fig 1) where a transistor (21) is connected to a voltage source (VDD) and a feedback node input to a first inverter (22) with a resistor (28) and capacitor (27) connected at the node, where the transistor receives an enable signal (signal at gate 21, which is based on input (2), column 1 lines 45-50). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the RC oscillator taught in Ishikawa with the transistor taught in Kucharewski in order to improve start up an RC oscillator.
As to claim 3, As would have been recognized by a person of ordinary skill in the art, the connection of the inverter string is done merely as intended use to couple a user desired output circuit to the RC oscillator.
As to claim 4, Ishikawa teaches wherein the first capacitor has a first capacitance (C1), wherein the second capacitor has a second capacitance (C2). It would be obvious to a person of ordinary skill in the art to have the capacitances be equal as it is mere matter of design choice to tuning and adjustable capacitor (C2) to a user desired capacitance.
As to claim 5, Ishikawa teaches wherein the first inverter, the second inverter, and the third inverter are each a complementary metal-oxide-semiconductor (CMOS) inverter (paragraph 23).
As to claim 6, Kucharewski the enable transistor (21). As would have been obvious to a person of ordinary skill in the art using a PMOS transistor is done merely as a design choice to choosing a user desired gate signal activation and the choice of transistor is merely a well known obvious equivalent.
As to claim 7, Kucharewski when the enable transistor is in an OPEN state, the first voltage at the first node is equal to the supply voltage, a second voltage at the second node is equal to the ground, a third voltage at the third node is equal to the supply voltage, and wherein a fourth voltage at the fourth node is equal to the ground (column 4 lines 8-35).
As to claim 8, Kucharewski teaches wherein, when the enable transistor changes from the OPEN state to a CLOSED state, the first voltage at the first node changes from the supply voltage to be equal to the ground, the second voltage at the second node changes from the ground to be equal to the supply voltage, the third voltage at the third node changes from the supply voltage to be equal to the ground, and wherein the fourth voltage at the fourth node changes from the ground to be equal to the supply voltage (column 4 lines 8-35).
As to claim 9, Ishikawa wherein the first inverter, the second inverter, and the third inverter each include a plurality of transistors (include PMOS and NMOS), and wherein all of the transistors in the first inverter, the second inverter, and the third inverter have the same oxide thickness (paragraph 23).
As to claim 10, Ishikawa teaches an electronic device comprising an oscillator circuit (fig 4) comprising: a first inverter (IV1) that is electrically connected to a supply voltage (VDD, paragraphs 23 and 36), a first node (connected to C2, C1, R0), and a second node (N1);
a second inverter (IV2) that is electrically connected to the supply voltage (VDD), the second node, and a third node N2);
a third inverter (IV3) that is electrically connected to the supply voltage (VDD), the third node N2), and a fourth node (N3);
a resistor (R0) that is electrically connected to the fourth node;
a first capacitor (C1) that is electrically connected to the third node (N2) and a sixth node that is electrically connected to the fifth node;
and a second capacitor (C2) that is electrically connected to the sixth node and a ground (Vss), wherein the first capacitor and the second capacitor form a capacitor divider (C1 and C2 form a divider), and wherein the capacitor divider limits a first voltage at the first node to a voltage range between the supply voltage and the ground (paragraphs 24, 25, and 36).
Ishikawa does not teach an enable transistors connected to the supply voltage and fifth node.
Kucharewski teaches an RC oscillator (fig 1) where a transistor (21) is connected to a voltage source (VDD) and a feedback node input to a first inverter (22) with a resistor (28) and capacitor (27) connected at the node, where the transistor receives an enable signal (signal at gate 21, which is based on input (2), column 1 lines 45-50). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the RC oscillator taught in Ishikawa with the transistor taught in Kucharewski in order to improve start up an RC oscillator.
As to claim 12, As would have been recognized by a person of ordinary skill in the art, the connection of the inverter string is done merely as intended use to couple a user desired output circuit to the RC oscillator.
As to claim 13, Ishikawa teaches wherein the first capacitor has a first capacitance (C1), wherein the second capacitor has a second capacitance (C2). It would be obvious to a person of ordinary skill in the art to have the capacitances be equal as it is mere matter of design choice to tuning and adjustable capacitor (C2) to a user desired capacitance.
As to claim 14, Ishikawa teaches wherein the first inverter, the second inverter, and the third inverter are each a complementary metal-oxide-semiconductor (CMOS) inverter (paragraph 23).
As to claim 15, Kucharewski the enable transistor (21). As would have been obvious to a person of ordinary skill in the art using a PMOS transistor is done merely as a design choice to choosing a user desired gate signal activation and the choice of transistor is merely a well-known obvious equivalent.
As to claim 16, Kucharewski when the enable transistor is in an OPEN state, the first voltage at the first node is equal to the supply voltage, a second voltage at the second node is equal to the ground, a third voltage at the third node is equal to the supply voltage, and wherein a fourth voltage at the fourth node is equal to the ground (column 4 lines 8-35).
As to claim 17, Kucharewski teaches wherein, when the enable transistor changes from the OPEN state to a CLOSED state, the first voltage at the first node changes from the supply voltage to be equal to the ground, the second voltage at the second node changes from the ground to be equal to the supply voltage, the third voltage at the third node changes from the supply voltage to be equal to the ground, and wherein the fourth voltage at the fourth node changes from the ground to be equal to the supply voltage (column 4 lines 8-35).
As to claim 18, Ishikawa wherein the first inverter, the second inverter, and the third inverter each include a plurality of transistors (include PMOS and NMOS), and wherein all of the transistors in the first inverter, the second inverter, and the third inverter have the same oxide thickness (paragraph 23).
As to claim 19, Ishikawa teaches method for operating an oscillator circuit (fig 4) comprising:
An oscillator circuit includes a plurality of inverters (IV1-IV3), a first capacitor (C1) a second capacitor (C2) forming a capacitor divider and a resistor (R0);
a first inverter (IV1) that is electrically connected to a supply voltage (VDD, paragraphs 23 and 36), a first node (connected to C2, C1, R0), and a second node (N1);
and wherein the capacitor divider limits a first voltage at the first node to a voltage range between the supply voltage and the ground (paragraphs 24, 25, and 36).
Ishikawa does not teach an enable transistors connected to the supply voltage and fifth node.
Kucharewski teaches an RC oscillator (fig 1) where a transistor (21) is connected to a voltage source (VDD) and a feedback node input to a first inverter (22) with a resistor (28) and capacitor (27) connected at the node, where the transistor receives an enable signal from control circuitry (signal at gate 21, which is based on input (2), column 1 lines 45-50) to change the transistor from open to closed or closed to open (column 4 lines 8-35). As such it would have been obvious to a person of ordinary skill in the art before the filing date of the invention to combine the RC oscillator taught in Ishikawa with the transistor taught in Kucharewski in order to improve start up an RC oscillator.
Allowable Subject Matter
Claims 2 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited prior art teaches or suggest having an additional enable switch to receive a second signal and the switch and the capacitor divider limits the voltage as is recited in claims 2 and 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY M SHIN whose telephone number is (571)270-7356. The examiner can normally be reached M-F 9am-6pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEFFREY M SHIN/Primary Examiner, Art Unit 2849