DETAILED ACTION
Status of Application
Claims 1-5 and 7-21 are pending in the present application.
Response to Arguments
Applicant's arguments filed 02/02/2026 have been fully considered but they are not persuasive. The reasons set forth below.
Applicant argues: (1) Rivers fails to discloses the amended features of claims 1 and 14 [remarks, pp. 6-7]; (2) claims 3, 5, and 8-13 are in condition for allowance for the additional subject matter they recite [remarks, p. 8].
The examiner respectfully disagrees with these arguments.
Regarding the first argument, the examiner notes that claim 1 is written in alternative form, where the language “at least one of” requires either feature A or feature B to be taught in the prior art. In this case, “the buffer width is determined based on at least one of assumed maximum values for input data processed by the set of arithmetic operations, and statistic parameters related to the input data processed by the set of arithmetic operations.” Cancelled claim 6 was directed towards “the buffer width is determined based on statistic parameters related to input data processed by the set of arithmetic operations.” In other words, the subject matter of claim 6 is now incorporated into claim 1, in the alternative form.
The examiner rejected now cancelled claim 6 over Rivers, in view of Karppanen, with Karppanen being cited to teach the limitation in question. The examiner did not find any arguments in applicant’s Remarks regarding the citation of Karppanen, hence the examiner is not persuaded by the general allegation that Karppanen does not address or overcome the deficiencies of Rivers [remarks, p. 8]. The examiner maintains that Karpannen teaches “the buffer width is determined based on statistic parameters related to input data processed by the set of arithmetic operations” [Karpannen, col. 5, lines 6-17, "whereupon the allocate buffer component may determine, based on the values of the dynamic maximum length data type input parameters, how much memory should be allocated in the string buffer"]. In addition, applicant’s Specification states: “The statistic parameters may indicate an input data type and/or distribution characteristics of the input data” and “The buffer width may be determined as a function with the statistic parameters as one or more parameters. Preferably, the function may include the word length as a further parameter”]. With this in mind, the examiner turns to Karpannen who discloses allocating memory to a buffer based on “dynamic maximum length data type input parameters.” Hence, Karpannen discloses data type and length used to allocate memory to a buffer, therefore Rivers in view of Karpannen, discloses the subject matter of amended claim 1.
Regarding the second argument, applicant has not provided specific arguments as to how the dependent claims distinguish themselves from the prior art references. Therefore, the prior art rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 8-9, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rivers et al (hereinafter Rivers), US 20020174319 A1, in view of Karppanen, US 9639460 B1.
Referring to claims 1 and 14, taking claim 1 as exemplary, Rivers discloses a method for dynamic buffer width allocation, comprising:
providing a memory with a plurality of memory slices [fig. 2, paragraph 23, “Each slice 230 consists of a portion of the register file RF 250”; hence register file 250 is a memory with a plurality of memory slices 230; paragraph 6, where a slice has a width of “8-bit (a byte) or a 16-bit (double byte) granularity”];
determining a buffer width for a set of arithmetic operations [fig. 2, paragraphs 6, 24, 27, 46-47, 49, “The determination of the width of an operation is performed after the decoder stage 205 in the pipeline”; “The slices shown here work either all in parallel when a full-width operation is executed, or only the lowermost slice(s) is (are) (minimum required number) enabled if the operation width is determined to be narrow. Slices are enabled on a cycle-by-cycle basis by the width detection (WD) logic 220 which uses information about the length of the operands kept in an RFtags module 210”; The RFtags module 210 can be a table that stores value bit information…about all operands; value bit information such as…register data width in bytes of the operand value; “where a slice can be of an 8-bit (a byte) or a 16-bit (double byte) granularity”; “FIG. 6 is a logic flow diagram of width determination WD for operations of the ALU (arithmetic logical unit)”; “FIG. 7 illustrates a width determination WD process for operands comprising source operands Src1 and Src2 and a result register Dst, as determined by the RFtags module 710 and WD logic 730”; “determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the operation”];
allocating a number of memory slices of the plurality of memory slices, the number of memory slices forming a buffer having at least the determined buffer width [fig. 2, paragraphs 24, 27, 46-47, 49, 57, “The determination of the width of an operation is performed after the decoder stage 205 in the pipeline”; “The slices shown here work either all in parallel when a full-width operation is executed, or only the lowermost slice(s) is (are) (minimum required number) enabled if the operation width is determined to be narrow; claim 17, “each slice comprises a portion of a register file, a portion of functional units, a portion of a memory path, a portion of a cache memory, and a portion of other resources required to perform operations in the processor”, “logic to determine a number of slices required to perform the operation based upon the width of one or more operands, the functionality of the operation, and the prediction of arithmetic overflow, logic to activate the slices required to perform the operation”; “Following the WD width determination stage, control signals flow from the WD logic 220 or 520 directly to enable dataflow and computation in the slices 230, FIG. 2, or 530, 540, FIG. 5, appropriately. The actual slices enabled per each cycle depends on the ‘width of the operation’ determined. Enabling and disabling is accomplished”]; and
performing the set of arithmetic operations using the buffer [figs. 1, 2, and 5 showing usage of the register file; paragraph 22, “the corresponding register values are read from a register file 150 and are input to an arithmetic logical unit 160 where the actual execution takes place, the output of which is stored back in a register file 150”].
Rivers does not explicitly disclose wherein the buffer width is determined based on at least one of assumed maximum values for input data processed by the set of arithmetic operations, and statistic parameters related to the input data processed by the set of arithmetic operations.
However, Karppanen discloses wherein the buffer width is determined based on at least one of assumed maximum values for input data processed by the set of arithmetic operations, and statistic parameters related to the input data processed by the set of arithmetic operations [col. 5, lines 6-17, “whereupon the allocate buffer component may determine, based on the values of the dynamic maximum length data type input parameters, how much memory should be allocated in the string buffer”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Karppanen in the method of Rivers to implement, wherein the buffer width is determined based on at least one of assumed maximum values for input data processed by the set of arithmetic operations, and statistic parameters related to the input data processed by the set of arithmetic operations, in order to improve performance by minimizing memory reallocation [Karppanen, col. 5, lines 46-47].
Referring to claims 2 and 16, taking claim 2 as exemplary, Rivers discloses the method of claim 1, wherein the memory enables a selective activation and deactivation of at least some of the memory slices of the plurality of memory slices [fig. 2, paragraphs 24, 27, 46-47, 49, 57, “logic to determine a number of slices required to perform the operation based upon the width of one or more operands, the functionality of the operation, and the prediction of arithmetic overflow, logic to activate the slices required to perform the operation”; “Following the WD width determination stage, control signals flow from the WD logic 220 or 520 directly to enable dataflow and computation in the slices 230, FIG. 2, or 530, 540, FIG. 5, appropriately. The actual slices enabled per each cycle depends on the ‘width of the operation’ determined. Enabling and disabling is accomplished”].
Referring to claims 4 and 17, taking claim 4 as exemplary, Rivers discloses the method according to claim 1, wherein the buffer width is determined based on a word length of values processed by the set of arithmetic operations [Abstract, “determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the operation”; fig. 2, paragraphs 6, 24, 27, 46-47, 49, “Slices are enabled on a cycle-by-cycle basis by the width detection (WD) logic 220 which uses information about the length of the operands kept in an RFtags module 210”].
Referring to claim 8, the modified Rivers discloses the method according to claim 1, further comprising receiving the statistic parameters related to the input data [Karppanen, col. 5, lines 6-17, “whereupon the allocate buffer component may determine, based on the values of the dynamic maximum length data type input parameters, how much memory should be allocated in the string buffer”].
Referring to claim 9, the modified Rivers discloses the method according to claim 8, wherein the statistic parameters are precalculated for the input data [Karppanen, col. 2, lines 17-18, default lengths may be determined for dynamic maximum length data types].
Referring to claim 15, Rivers discloses an apparatus, comprising:
a dynamic memory according to claim 14 [fig. 2, paragraphs 24, 27, 46-47, 49, 57, “The actual slices enabled per each cycle depends on the ‘width of the operation’ determined. Enabling and disabling is accomplished”].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rivers, in view of Karppanen, as applied to claim 1 above, and further in view of Jeon, US 20220113885 A1.
Referring to claim 3, the modified Rivers does not explicitly disclose the method of claim 1, further comprising deactivating unallocated memory slices of the plurality of memory slices.
However, Jeon discloses deactivating unallocated memory slices of the plurality of memory slices [paragraph 59, “A memory block allocated for a specific ZNS can be released according to garbage collection, and another free block can be newly allocated for the specific ZNS. Or, when the specific ZNS is deactivated, the at least some memory blocks of the deactivated ZNS may become unallocated for any ZNS”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Jeon in the method of the modified Rivers to implement, deactivating unallocated memory slices of the plurality of memory slices, in order to increase efficiency of garbage collection and decrease a frequency of performing garbage collection, which can increase a lifespan of the memory device [Jeon, paragraph 65].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rivers, in view of Karppanen, as applied to claim 1 above, in view of Chiraz, US 6411302 B1.
Referring to claim 5, the modified Rivers does not explicitly disclose the method according to any one of the preceding claims claim 1, wherein the buffer width is determined based on a number of results of the set of arithmetic operations.
However, Chiraz discloses wherein the buffer width is determined based on a number of results of the set of arithmetic operations [col. 20, lines 15-25, fig. 19, determines the size of the extra memory area based on the number of loop iterations].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Chiraz in the method of the modified Rivers to implement, wherein the buffer width is determined based on a number of results of the set of arithmetic operations, in order to provide increased flexibility in configuring various arrangements of buffers and also allows optimum use of memory [Chiraz, col. 33, lines 1-3].
Claim(s) 7, 10, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rivers, in view of Karppanen, as applied to claims 1 and 14 above, and further in view of Fruchter, US 20210089458 A1.
Referring to claims 7 and 18, taking claim 7 as exemplary, the modified Rivers does not explicitly disclose the method according to claim 1, further comprising collecting the statistic parameters during processing of the set of arithmetic operations in real time.
However, Fruchter discloses collecting the statistic parameters during processing of the set of arithmetic operations in real time [paragraphs 73, 150, 152, “By using a dynamically allocated buffer memory with a flexible size, the system may have optimal memory usage by avoiding buffer overflow and reducing buffer memory waste. In particular embodiments, the system may determine the buffer size (and dynamically allocate the corresponding memory space) based on the size of the data chunks (e.g., a frame, a portion of a frame, a surface size, a slice, a tile, a tile row) that need to be buffered”, “one or more computer systems 800 may perform in real time or in batch mode one or more steps of one or more methods described or illustrated herein”; “Where appropriate, processor 802 may include one or more arithmetic logic units (ALUs)”].
Referring to claims 10 and 19, taking claim 10 as exemplary, the modified Rivers does not explicitly disclose the method according to claim 1, further comprising monitoring at least one value to be stored in the buffer, determining that the at least one value exceeds a threshold, and dynamically allocating at least one further memory slice of the plurality of memory slices for the buffer.
However, Fruchter discloses monitoring at least one value to be stored in the buffer, determining that the at least one value exceeds a threshold, and dynamically allocating at least one further memory slice of the plurality of memory slices for the buffer [paragraph 73, “By using a dynamically allocated buffer memory with a flexible size, the system may have optimal memory usage by avoiding buffer overflow and reducing buffer memory waste. In particular embodiments, the system may determine the buffer size (and dynamically allocate the corresponding memory space) based on the size of the data chunks (e.g., a frame, a portion of a frame, a surface size, a slice, a tile, a tile row) that need to be buffered”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Fruchter in the method of the modified Rivers to implement, monitoring at least one value to be stored in the buffer, determining that the at least one value exceeds a threshold, and dynamically allocating at least one further memory slice of the plurality of memory slices for the buffer, in order to avoid buffer overflow and reduce buffer memory waste [Fruchter, paragraph 73].
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rivers, in view of Karppanen, as applied to claims 1 and 14 above, and further in view of Bocklet et al (hereinafter Bocklet), US 20190043488 A1.
Referring to claims 11 and 20, taking claim 11 as exemplary, the modified Rivers does not explicitly disclose the method according to claim 1, wherein the set of arithmetic operations includes a plurality of multiply-accumulate operations, wherein results of the plurality of multiply-accumulate operations are accumulated in the buffer.
However, Bocklet discloses wherein the set of arithmetic operations includes a plurality of multiply-accumulate operations, wherein results of the plurality of multiply-accumulate operations are accumulated in the buffer [paragraphs 34, 124, “a dynamic audio data buffer size (or length management) control system 1300 is provided for audio data buffer size management while performing autonomous neural network acceleration”; “Herein, a neural network accelerator (NNA) refers to a specific-purpose processor that is specifically arranged to process a neural network. Such an NNA at least has specific logic hardware for vectors of input data to be propagated through a neural network, input weights for nodes on the network, and input bias and/or constants to be applied, as well as a propagation circuit such as a multiply-accumulate circuit for example, and an activation function unit”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Bocklet in the method of the modified Rivers to implement, wherein the set of arithmetic operations includes a plurality of multiply-accumulate operations, wherein results of the plurality of multiply-accumulate operations are accumulated in the buffer, in order to provide advantages in terms of computational efficiency and power usage [Bocklet, paragraph 58].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rivers, in view of Karppanen, as applied to claim 1 above, and further in view of Wang et al (hereinafter Wang), US 20100165842 A1.
Referring to claim 13, the modified Rivers does not explicitly disclose the method according to claim 1, further comprising allocating a further number of memory slices of the plurality of memory slices for a further buffer.
However, Wang discloses allocating a further number of memory slices of the plurality of memory slices for a further buffer [paragraph 7, claim 11, fig. 1, The credit management unit is configured to dynamically adjust a first amount of the buffer memory used to store packet headers and a second amount of the buffer memory used to store the packet data responsive to a size of the packet data in one or more received packets, and wherein the credit management unit is configured to free data credits and header credits to a transmitter on the interface responsive to the dynamic adjustments; see fig. 1 showing element 32 equivalent to a further buffer].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Wang in the method of the modified Rivers to implement, allocating a further number of memory slices of the plurality of memory slices for a further buffer, in order to permit more efficient usage of the buffer memory [Wang, paragraph 49].
Allowable Subject Matter
Claims 12 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the plurality of multiply-accumulate operations include multiplying a plurality of weights with input data, wherein the buffer width is determined based on values of the plurality of weights and the assumed maximum values for the input data, in combination with other recited limitations in claim 12.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the plurality of multiply-accumulate operations include multiplying a plurality of weights with input data, and the buffer width is determined based on values of the plurality of weights and the assumed maximum values for the input data, in combination with other recited limitations in claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/Primary Examiner, Art Unit 2181
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