DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) was/were submitted on 08/12/2024 and 03/16/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, all information disclosure statements are being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a control unit for providing the plurality of control signals to the plurality of quantum computing units” in claim 1.
“a signal division arrangement for transmitting the plurality of control signals originating from the control unit to the plurality of quantum computing units” in claim 1.
“a read-out unit configured to: obtain the at least one output signal from each quantum computing unit in the plurality of quantum computing units” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 12-13, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Carine et al. (“Multi-core fiber integrated multi-port beamsplitters for quantum information processing”).
Regarding claim 1, Carine teaches
An arrangement for quantum computing, comprising: a plurality of quantum computing units, each quantum computing unit comprising a plurality of qubits arranged to perform a quantum computation according to a plurality of control signals provided to the quantum computing unit and to provide at least one output signal according to a result of the quantum computation (Carine, page 5, Fig. 3, “PMs”. Carine, page 6, “An implementation of the MDI RNG protocol with 4-dimensional quantum states involves the state preparation device that can randomly prepare five different states.” Carine, page 4, “Each path contains two fiber-pigtailed LiNbO3 phase modulators (PM) with 10 GHz bandwidth. This allows us to prepare and measure a more general class of path qudit states.” Examiner notes the PMs are the plurality of quantum computing units.)
a control unit for providing the plurality of control signals to the plurality of quantum computing units (Carine, page 4, “The first set of PMs is also controlled by the FPGA1 unit and are used for state preparation.” Carine, page 5, Fig. 3, “FPGA1”.)
a signal division arrangement for transmitting the plurality of control signals originating from the control unit to the plurality of quantum computing units (Carine, page 5, Fig. 3, “DEMUX” and “MCF MBS” sections in FPGA1.)
wherein the signal division arrangement is configured to divide each control signal in the plurality of control signals originating from the control unit to each quantum computing unit in the plurality of quantum computing units (Carine, page 5, Fig. 3, “MCF MBS” into “DEMUX”. Examiner notes DEMUX is configured to divide each signal and sends each signal to a PM.)
wherein the control unit is configured to, via the plurality of control signals and the signal division arrangement, cause each quantum computing unit in the plurality of the quantum computing units to execute a separate instance of the quantum computation (Carine, page 5, Fig. 3, “PMs”, “FPGA1”. Carine, page 4, “Each path contains two fiber-pigtailed LiNbO3 phase modulators (PM) with 10 GHz bandwidth. This allows us to prepare and measure a more general class of path qudit states.” Carine, page 4, “The first set of PMs is also controlled by the FPGA1 unit and are used for state preparation.”)
and a read-out unit configured to: obtain the at least one output signal from each quantum computing unit in the plurality of quantum computing units (Carine, page 5, Fig. 3, “Outcome measurement”, “FPGA2”. Examiner notes the read-out unit is FPGA2 (measuring unit) which obtains signals from each PM in FPGA1.)
and perform at least one statistical operation based on the output signals, thus obtaining an ensemble quantum computation result (Carine, page 7, “Notice that, in our experiment we observe ten measurement outcomes: four single clicks corresponding to photon detection at one of the four detectors Di (i = 0,...,3), and six co incidence detections between detectors Di and Dj with i= j. The statistics of all these events are taken into consideration in the randomness estimation.” Carine, page 7, “We continuously verify that the protocol is working properly through the average success probability of identify ing the states ωx (i.e., ¯p = 1 4 3 x=0 p(x|ρx). If p> 0.992, then the random bit sequence is recorded.” Carine, page 4, “Finally, the state projection is done by another 4×4 MBS, whose input is first converted from the four individual single-mode arms to a single 4-core fiber by a third DEMUX unit. Considering the 4×4 MCF MBS matrix representation, and the action of the second set of PMs, one can show that the form of the measurement basis states at the end of the circuit are given by
PNG
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131
334
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.” Examiner notes that the third demultiplexer unit converts the input of four individual signals to a single one using equation 4, therefore obtaining an ensemble quantum computation result.)
Regarding claim 2, Carine teaches
The arrangement according to claim 1, wherein each quantum computing unit in the plurality of quantum computing units corresponds to a quantum processing unit, QPU, a core in a multi-core QPU, or a sub-unit of a QPU (Carine, page 4, “A programmable quantum circuit allows one to prepare different quantum states and measure them with different bases in a controllable way. Now, we show (i) how the MCF MBSs can be used to build a multi-arm MZ interferometer, and (ii) how off-the-shelf telecommunication components can be incorporated into it for implement ing an efficient quantum circuit.” Carine, page 4, “This device is composed of four independent single-mode fibers connected to a 4 core MCF. Each single-mode fiber is mapped to one of the cores of the MCF fiber. In our system, after the first DEMUX, only one of the MCF cores is illuminated, which is shown schematically in Fig. 3.” Carine, page 5, Fig. 3.)
Regarding claim 3, Carine teaches
The arrangement according to claim 1, wherein the signal division arrangement is configured to divide each control signal in the plurality of control signals originating from the control unit to each quantum computing unit in the plurality of quantum computing units (101) using at least one T-junction, at least one power divider, at least one Wilkinson power divider, at least one directional coupler, and/or at least one hybrid coupler (Carine, page 3, “The cores will consequently be brought together, and due to evanescent coupling, light will leak from one core to the others, similar to what is obtained in a standard fiber-optical bi directional coupler (See Fig. 1b).” Carine, page 3, Fig. 1b.)
Regarding claim 4, Carine teaches
The arrangement according to claim 1, further comprising a tuning arrangement configured to adjust at least one property of the plurality of control signals divided by the signal division arrangement, wherein the at least one property comprises at least one of: frequency, amplitude, phase, and/or relative timing (Carine, page 4, “we note that while only three phase modulators are needed for each set, we opted to maintain the fourth on.” Carine, page 4, “Nevertheless, long term phase drifts are present and we implemented a con trol system to actively compensate them. The control is implemented by FPGA2 and it is based on a perturb and observe power point tracking method [85]. More specifically, each applied phase φB k can be decomposed as φB k = φbias k, where the employed voltage driver is capable of supplying the sum of two independent volt ages Vbias and Vmod. Vbias is a low-speed signal used to control φbias k ,and this is intended to compensate a given phase drift φn k. Vmod is the high-speed signal for modulating the desired phase φmod k . Since the total relative phase at the kth arm is φB k = φbias k +φmod k +φn k, the phase drift compensation algorithm running in FPGA2 will perturb the kth phase modulator to make φbias k =−φn k, such that the phase noise is eliminated.” Examiner notes the tuning arrangements are the phase modulators, which modify the phase of received signals.)
Regarding claim 5, Carine teaches
The arrangement according to claim 4, wherein the tuning arrangement further comprises at least one voltage-controlled attenuator configured to adjust at least one control signal in the plurality of control signals divided by the signal division arrangement (Carine, page 4, “More k +φmod specifically, each applied phase φB k can be decomposed as φB k = φbias k ,where the employed voltage driver is capable of supplying the sum of two independent voltages Vbias and Vmod. Vbias is a low-speed signal used to control φbias k ,and this is intended to compensate a given phase drift φn k. Vmod is the high-speed signal for modulating the desired phase φmod k . Since the total relative phase at the kth arm is φB k = φbias k +φmod k +φn k, the phase drift compensation algorithm running in FPGA2 will perturb the kth phase modulator to make φbias k =−φn k, such that the phase noise is eliminated.” Examiner notes the voltage-controlled attenuator is the voltage driver, which adjusts the control signal (modulating signal phase) and is part of the tuning arrangement (phase modulator).)
Regarding claim 12, Carine teaches
The arrangement according to claim 1, wherein the plurality of qubits comprises superconducting qubits (Carine, page 2, “we note that the average insertion loss for the fabricated 4×4 (7×7) MBSs is only 4.3% (9.0%), which allows for a qudit transmission of 42% through the programmable circuit and a corresponding overall detection efficiency that can reach at least 35% with commercially available superconducting single-photon detectors (efficiency > 85%).”)
Regarding claim 13, Carine teaches
The arrangement according to claim 1, wherein the at least one statistical operation comprises at least one of: a mean, a variance, and/or cross-entropy (Carine, page 6, “b) Observed average success probability for each zone E4. Error bars lie within the experimental point representation. c) Average obtained randomness per experimental round for each zone E1. Error bars lie within the star symbols. The dashed line represents the theoretical upper bound allowed for binary RNG protocols.” Carine, page 6, Fig. 5b and 5c. Examiner notes the statistical operation includes average obtained randomness and average success probability for the signals recorded.)
Regarding claim 15, Carine teaches
A quantum computing system comprising a plurality of arrangements according to claim 1 (Carine, page 5, Fig. 3. Carine, page 4, “A programmable quantum circuit allows one to prepare different quantum states and measure them with different bases in a controllable way. Now, we show (i) how the MCF MBSs can be used to build a multi-arm MZ interferometer, and (ii) how off-the-shelf telecommunication components can be incorporated into it for implement ing an efficient quantum circuit.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6, 10-11 is/are rejected under 35 U.S.C. 103 as being anticipated by Carine in view of Hornibrook et al. (“Frequency multiplexing for readout of spin qubits”).
Regarding claim 6, Carine teaches The arrangement according to claim 5. Carine does not, but Hornibrook teaches
wherein the at least one voltage-controlled attenuator comprises at least one high-electron mobility transistor, at least one tuneable reactive impedance element, at least one superconducting quantum interference device, and/or at least one varactor diode (Hornibrook, page 4, “The 10 channels are defined using inductors Li with values between 60 nH and 250 nH that form a resonant circuit with parasitic capacitance Cp as described above. Each channel again integrates a bias tee, needed for independent biasing of the gate sensors. Operation of the 10-channel chip is tested at 4.2K using a series of high electron mobility transistors (HEMTs) fabricated from a GaAs/Al0.3Ga0.7As heterostructure and connected to the MUX chip via bondwires.” Examiner notes the resonant circuit is the voltage-controlled attenuator, which adjusts resonant frequency, and the resonant circuit (chip) comprises high-electron mobility transistors (HEMTs).)
Carine and Hornibrook teach a quantum system that multiplexes signal frequencies and thus are analogous to the claimed invention. It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the application to have modified Carine to use a high-electron mobility transistor like Hornibrook. Doing so would have been advantageous because the approach “advances previous demonstrations by lithographically integrating the feed-lines, bias tees, and resonators, which are fabricated on a sapphire chip using low-loss superconducting niobium. By putting these components on-chip, the size of the entire MUX circuit is reduced far below the wavelength of the rf signals, suppressing impedance mismatch from the unintentional formation of stub-networks that otherwise occur in macroscale multi-channel feedlines” (Hornibrook, page 2).
Regarding claim 10, Carine teaches The arrangement according to claim 1. Carine does not, but Hornibrook teaches
wherein each quantum computing unit in the plurality of quantum computing units further comprises a plurality of frequency tuning elements configured to tune qubit frequencies of the plurality of qubits according to a frequency tuning signal (Hornibrook, page 2, “Here, we report an on-chip approach to frequency multiplexing for the simultaneous readout of scaled-up spin qubit devices.” Hornibrook, page 3, Fig. 1e. Hornibrook, page 3, “The inductors (red, Fig. 1(e)), used in both the resonant circuit and bias tees, are spiral shaped with critical dimension of 3lm. The measured inductances (170, 250, and 400 nH) are in agreement with analytical calculations based on their geometry. The self-resonance frequency of all the inductors is increased by over-etching the sapphire dielectric between adjacent turns, decreasing the effective dielectric constant and reducing the capacitance.” Examiner notes the frequency of the inductors can be increased and thus tuned when measuring qubit frequencies.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Carine with the teachings of Hornibrook for the same reasons disclosed in claim 6.
Regarding claim 11, Carine teaches The arrangement according to claim 1. Carine does not, but Hornibrook teaches
wherein each quantum computing unit in the plurality of quantum computing units further comprises a plurality of capacitance tuning elements configured to tune capacitances of the plurality of qubits according to a capacitance tuning signal (Hornibrook, page 2, “Here, we report an on-chip approach to frequency multiplexing for the simultaneous readout of scaled-up spin qubit devices.” Hornibrook, page 3, Fig. 1e. Hornibrook, page 3, “The inductors (red, Fig. 1(e)), used in both the resonant circuit and bias tees, are spiral shaped with critical dimension of 3lm. The measured inductances (170, 250, and 400 nH) are in agreement with analytical calculations based on their geometry. The self-resonance frequency of all the inductors is increased by over-etching the sapphire dielectric between adjacent turns, decreasing the effective dielectric constant and reducing the capacitance.” Examiner notes the capacitance of the inductors can be reduced and thus tuned when measuring qubit frequencies.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Carine with the teachings of Hornibrook for the same reasons disclosed in claim 6.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being anticipated by Carine in view of Bodog et al. (“Optimization of multiplexed single-photon sources operated with photon-number-resolving detectors”).
Regarding claim 7, Carine teaches The arrangement according to claim 1. Carine does not, but Bodog teaches
wherein the output signals from the plurality of quantum computing units are time-multiplexed and the read-out unit is further configured to obtain the at least one output signal from each quantum computing unit in the plurality of quantum computing units according to the time-multiplexing (Bodog, page 1, “We analyze various spatially and time-multiplexed periodic single-photon source arrangements with photon-number-resolving detectors, partly to identify the cases when they outperform those with threshold detectors. We develop a full statistical description of these arrangements in order to optimize such systems with respect to maximal single-photon probability, taking into account all relevant loss mechanisms. The model is suitable for the de scription of all spatial and time multiplexing schemes.”)
Carine and Bodog teach a quantum system that multiplexes signal frequencies and thus are analogous to the claimed invention. It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the application to have modified Carine to utilize time-multiplexing for the plurality of output signals like Bodog. Doing so would have been advantageous because the approach because “the system with binary bulk time multiplexing and single-photon detectors offers the highest single-photon probability which is PSPD = 0.907” (Bodog, page 9).
Regarding claim 8, Carine and Bodog teach The arrangement according to claim 7. Bodog further teaches
further comprising delay lines coupled to the plurality of quantum computing units and configured to time- multiplex the output signals from the plurality of quantum computing units (Bodog, page 3, “the heralded photons are directed to switchable delay lines with different time lengths (∆τ, 2∆τ, 4∆τ ... ) which are multiples of powers of 2. Signal photons heralded in the nth time slot travel only through those delay lines whose length corresponds to the nonzero digits in the binary representation of the time delay (N − n)∆τ.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Carine with the teachings of Bodog for the same reasons disclosed in claim 7.
Claim(s) 9, 14 is/are rejected under 35 U.S.C. 103 as being anticipated by Carine in view of Chapman et al. (“General purpose multiplexing device for cryogenic microwave systems”).
Regarding claim 9, Carine teaches The arrangement according to claim 1. Carine does not, but Chapman teaches
wherein the read-out unit further comprises a summing arrangement and wherein the read- out unit is configured to perform the at least one statistical operation based on the output signals by coherently summing the output signals via the summing arrangement (Chapman, page 3, “Recombination of the multiplexed signals (indicated by the summation box R) may be accomplished with a microwave hybrid.” Chapman, page 5, “These microwave channels are then fed into a cryostat and modulated by separate TIBs. During one digital period, the two TIBs are programmed to transmit and invert according to distinct Walsh codes wn and wm. The outputs of the TIBs are summed and directed out of the cryostat through a single microwave receiver. The final mixed down voltage is the sum of two Walsh-modulated analog square waves, where the upper and lower values of the two square waves correspond to the logical 1 and 0 of the original digital bits.” Examiner notes the signals are multiplexed and summed together.)
Carine and Chapman teach a quantum system that multiplexes signal frequencies and thus are analogous to the claimed invention. It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the application to have modified Carine to utilize a summing arrangement to multiplex the output signals like Chapman. Doing so would have been advantageous because the approach because summing the outputs “avoids the loss of a matched recombination network” (Chapman, page 3).
Regarding claim 14, Carine teaches The arrangement according to claim 1. Carine does not, but Chapman teaches
further comprising a cryostat, wherein the plurality of quantum computing units and the signal division arrangement are located inside the cryostat (Chapman, page 5, “These microwave channels are then fed into a cryostat and modulated by separate TIBs. During one digital period, the two TIBs are programmed to transmit and invert accord ing to distinct Walsh codes wn and wm. The outputs of the TIBs are summed and directed out of the cryostat through a single microwave receiver. The final mixed down voltage is the sum of two Walsh-modulated analog square waves, where the upper and lower values of the two square waves correspond to the logical 1 and 0 of the original digital bits.”)
Carine and Chapman teach a quantum system that multiplexes signal frequencies and thus are analogous to the claimed invention. It would have been obvious to one having ordinary skill in the art prior to the effective filing date of the application to have modified Carine to utilize a cryostat like Chapman. Doing so would have been obvious because utilizing a cryostat is a standard approach in quantum systems, and is advantageous because a cryostat can maintain extremely low temperatures which keeps qubits stable long enough to perform calculations and suppress thermal noise.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Zared O. Cohen whose telephone number is (571)270-0531. The examiner can normally be reached M-Th, 8am to 5pm ET.
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/Z.O.C./Examiner, Art Unit 2148 /MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148
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