DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are present for examination.
Priority
This application is a 371 of PCT/CN2023/133275 filed on 11/22/2023.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/05/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 13, 15, 16, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (US 2024/0071303), hereinafter as Huang.
RE claim 1, Huang discloses the invention substantially as claimed.
Huang discloses that a pixel circuit (see figures 1&2 and sections [0044], [0046]; i.e., pixel circuit 101), configured to drive a light-emitting element to emit light in a plurality of frame periods which has a target refresh frequency, each of the frame periods comprising a refresh frame and at least one hold frame (see figures 2&4 and sections [0052], 0053], [0056], [0057]; i.e., OLED to emit light in a plurality of frame periods, such as many refresh frames FR and many holding frames FH, with different refresh frequencies corresponding to different reset voltages Vreset, wherein each of the different refresh frequencies being a target refresh frequency), the pixel circuit comprising: a first control circuit, respectively coupled to a first gate control terminal, a second gate control terminal, a data terminal, a first node, a second node, and a third node, wherein the first control circuit is configured to control switching on and off of a connection between the first node and the third node in response to a first gate control signal provided by the first gate control terminal, and configured to control switching on and off of a connection between the data terminal and the second node in response to a second gate control signal provided by the second gate control terminal (see figure 22 and section [0139]; i.e., first control circuit M3, respectively coupled to first node N1, second node N2, third node N3, through its gate control terminal, first electrode, second electrode, wherein the first control circuit M3 configured to control switching on/off of a connection between the first node N1 and third node N3 in response to a first gate control signal provided by the first gate control terminal connected to node N1, and configured to control switching on/off of a connection between the data terminal M2 and the second node N2 in response to a second gate control signal provided by the second gate control terminal, e.g., the gate terminal of S2); a second control circuit, respectively coupled to a first reset terminal, a second reset terminal, a first initial terminal, a second initial terminal, a third initial terminal, the second node, the third node, and a fourth node, wherein second control circuit is configured to control switching on and off of a connection between the first initial terminal and the third node in response to a first reset signal provided by the first reset terminal, and a control switching on/off of a connection between the second initial terminal and the fourth node and control switching on/off of a connection between the third initial terminal and the second node in response to a second reset signal provided by the second reset terminal (see figure 2 and section [013]; i.e., second control circuit M6, respectively coupled to first reset terminal M7, second reset terminal M5, first initial terminal connected to second node N2, second initial terminal connected to third node N3, third initial terminal connected to fourth node N4, wherein the second control circuit M6 being configured to control switching on/off of a connection between the first initial terminal and third node N3 in response to a first reset signal provided by the first reset terminal M7, and control switching on/off of a connection between the second initial terminal and fourth node N4, and control switching on/off of a connection between the third initial terminal and second node N2 in response to a second reset signal provided by the second reset terminal M5); a third control circuit, respectively coupled to a light-emitting control terminal, a driving power supply terminal, the second node, the third node, and the fourth node, wherein the third control circuit is configured to control switching on/off of a connection between the driving power supply terminal and the second node and switching on and off of a connection between the third node and the fourth node in response to a light-emitting control signal provided by the light-emitting control terminal, the fourth node being coupled to the light-emitting element (see figure 22 and section [0139]; i.e., third control circuit M1, respectively coupled to light-emitting control terminal EMIT, driving power supply terminal PVDD, second node N2, third node N3, fourth node N4, wherein the third control circuit M1 being configured to control switching on/off of a connection between driving power terminal PVDD and second node N2, and switching on/off of a connection between third node N3 and fourth node N4 in response to a light-emitting control signal provided by the light-emitting control terminal EMIT, the fourth node N4 coupled to light-emitting element OLED); and a driving circuit, respectively coupled to the first node, the second node, and the third node, wherein the driving circuit is configured to transmit a driving signal to the third node based on a potential of the third node a potential of the second node (see figure 22 and section [0139]; i.e., the driving circuit M3, respectively coupled to first node N1, second node N2, third node N3, wherein the driving circuit M3 being configured to transmit a driving signal to third node N3 based on a potential of first node N1 and a potential of second node N2); wherein the connection between the first initial terminal and the first node and the connection between the third initial terminal and the third node are sequentially controlled to be switched on in the refresh frame, so that a first initial signal and a third initial signal are sequentially transmitted to the first node and the second node through the first initial terminal and the third initial terminal, respectively, wherein a potential difference between the first initial signal and the third initial signal that are transmitted is greater than or equal to a potential difference threshold (see figures 22/23 and sections [0139], [0140]-[0145]; i.e., the connection between first initial terminal M5 and first node N1 and the connection between the third initial terminal M4 and third node N3 are sequentially controlled to be switched on in the refresh frame FR by scan signal S1N, the voltage of first node N1 is reset/refreshed by the threshold/reference voltage Vref1 in time sequence t1-t4, in second time period t2 of the refresh frame FR, the first control signal S1 is turned on, the voltage of the first electrode is reset/refreshed by the reset signal Vreset and the first scan signal S2N is turned on; in this way, first node N1 and third node N3 can be turned on, such that the driving transistor M3 can be reversed biased).
It may or may not exist any difference in terms of circuitry connections or wirings between the instant claim and disclosure of Huang; however, the particular placement of a contact or connections or wirings in a conductivity measuring device was held to be an obvious matter of design choice. (see In re Kuhle, 526 F.2d 553, 188 USPQ 7, CCPA 1975).
RE claims 2 and 16, Huang discloses the invention substantially as claimed.
However, Huang does not specifically disclose that the potential difference threshold is -9v.
The use of mathematical formula or ranges (i.e., the potential difference threshold is -9v) are akin to optimizing the values of a result effective variable. Therefore, determining the optimal value of a result effective variable would have been obvious and ordinarily within the skill of the art. In re Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980).
RE claims 3, 17 and 20, Huang in view of rationale above disclose that wherein the first control circuit comprises: a first transistor and a second transistor; the second control circuit comprises: a third transistor, a fourth transistor, and a fifth transistor, the third control circuit comprises: a sixth transistor and a seventh transistor; and the driving circuit comprises: an eighth transistor (see figure 22 and its associated depictions); wherein a gate of the first transistor is coupled to the first gate control terminal, a first electrode of the first transistor is coupled to the third node, and a second electrode of the first transistor is coupled to the first node (see figure 22 and its associated depictions; i.e., transistor M4); a gate of the second transistor is coupled to the second gate control terminal, a first electrode of the second transistor is coupled to the data terminal, and a second electrode of the second transistor is coupled to the second node (see figure 22 and its associated depictions; i.e., transistor M2); a gate of the third transistor is coupled to the first reset terminal, a first electrode of the third transistor is coupled to the first initial terminal, and a second electrode of the third transistor is coupled to the third node (see figure 22 and its associated depictions; i.e., transistor M6); a gate of the fourth transistor is coupled to the second reset terminal, a first electrode of the fourth transistor coupled to the second initial terminal, and a second electrode of the fourth transistor is coupled to the fourth node (see figure 22 and its associated depictions; i.e., transistor M7); a gate of the fifth transistor is coupled to the second reset terminal, a first electrode of the fifth transistor is coupled to the third initial terminal, and a second electrode of the fifth transistor is coupled to the second node (see figure 22 and its associated depictions; i.e., transistor M3); a gate of the sixth transistor is coupled to the light-emitting control terminal, a first electrode of the sixth transistor is coupled to the driving power supply terminal, and a second electrode of the sixth transistor is coupled to the second node (see figure 22 and its associated depictions; i.e., transistor M1); a gate of the seventh transistor is coupled to the light-emitting control terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to the fourth node (see figure 22 and its associated depictions; i.e., transistor M6); a gate of eighth transistor is coupled to the first node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of eighth is coupled to the third node (see figure 22 and its associated depictions; i.e., transistor M3); the pixel circuit further comprising: a storage capacitor connected between the driving power supply terminal and the first node (see figure 22 and its associated depictions; i.e., storage capacitor Cst).
RE claim 13, Huang in view of rationale above disclose that a display panel, comprising: a substrate and a plurality of pixels disposed on the substrate; wherein each of the plurality of pixels comprises: a light-emitting element, wherein the pixel circuit is coupled to the light-emitting element, and is configured to drive the light-emitting element to emit light (see figures 1/22 and its associated depictions; i.e., display panel 100, pixel circuit 101, light-emitting element OLED).
RE claim 15, Huang in view of rationale above disclose that a display device, comprising: a power supply assembly, and the display panel, wherein the power supply assembly is coupled to display panel, and is configured to supply power to the display panel (see figures 1&22 and its associated depictions; i.e., display panel 100, power supply assembly PVDD).
Allowable Subject Matter
Claims 4-12, 14, 18, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al (USPN 12,444,364)
Wang et al (US 2025/0285591)
Lin et al (USPN 10,304,378)
Zhang (USPN 11,538,412)
Any inquiry concerning this communication from the examiner should be directed to whose telephone number is 571-272-7565. The examiner can normally be reached on weekdays from 2:0 pm to 10:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached on 571-272-0666. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300 for regular communications and 571-273-7565 for After Final communications.
Informal regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docs for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000 (IN USA).
/FRED TZENG/ Primary Examiner, Art Unit 2625
FFT
September 17, 2026
Prosecution Insights