Prosecution Insights
Last updated: April 19, 2026
Application No. 18/837,878

AMPLIFIER

Non-Final OA §103
Filed
Aug 12, 2024
Examiner
OJO, OYESOLA C
Art Unit
2695
Tech Center
2600 — Communications
Assignee
Focusrite Audio Engineering Limited
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
93%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
587 granted / 715 resolved
+20.1% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
21 currently pending
Career history
736
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
56.8%
+16.8% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 715 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 14, 17, 19-20 and 22 are cancelled Claims 1-6, 8-13, 21 and 23-25 are rejected Claims 7, 15-16 and 18 are objected to Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-6, 8-13, 21 and 23-25 is/are is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakai (US PUB 20130243223, hereinafter Sakai) in view of Gagon (US PAT 5736897, hereinafter Gagon). Regarding Claim 1, Sakai discloses an amplifier for amplifying audio signals (see at least the abstract and figure 1) comprising: a plurality of stages (e.g. plurality of amplifiers stages AMP1 to AMP4), at least two of the stages of the plurality of stages being connected in series (e.g. AMP3 and AMP4 are in series), (see figure 2) and each of the at least two stages being a gain stage, the at least two stages being arranged, in use, to apply gain to an input signal provided to the amplifier (e.g. each of the AMP1 to AMP4 is a gain stage for applying gain to an input signal from an audio source 2), (see Sakai, [0032]-[0035], also figures 1-2). Saiki does not explicitly disclose: each provided by a preamplifier stage. However, Gagon in the same field of endeavor teaches an amplifier (e.g. amplifier module 200), (see figure 4), comprising a plurality of stages (e.g. plurality of amplifier stages 237, 240 and 250), at least two of the stages of the plurality of stages being connected in series (see figure 4), and each of the at least two stages being a gain stage, each provided by a preamplifier stage (e.g. each of amplifier stages 237, 240 and 250 is a preamplifier), (see Gagon, column 4 lines 12-30, also figures 3 and 4). Therefore, it would have been obvious to any person having an ordinary skill in the art before the effective filing date of the present invention to incorporate providing each of a first stage and a second stage of an amplifier by a preamplifier as taught by Gagon in the teachings of Sakai in order to generate additively amplified composite signal with enhanced output features. Regarding Claim 2, Sakai as modified by Gagon discloses the amplifier according to claim 1, wherein the amplifier is a preamplifier (e.g. AMP1 functions as a preamplifier for the system), (see Sakai, figure 2). Regarding Claim 3, Sakai as modified by Gagon discloses the amplifier according to claim 1, wherein the plurality of stages includes an analogue to digital converter, ADC, driver stage (e.g. an ADC 10), (see Sakai, figure 2). Regarding Claim 4, Sakai as modified by Gagon discloses the amplifier according to claim 3, wherein at least one stage of the at least two stages and the ADC driver are part of an integrated circuit (e.g. the amplifiers and ADC are formed into an integrated circuit 100), (see Sakai, [0032], and figures 1- 2). Regarding Claim 5, Sakai as modified by Gagon discloses the amplifier according to claim 4, wherein a further at least one stage of the at least two stages is connected between a first output (e.g. OUT-terminal) of the integrated circuit and a first input (e.g. IN-terminal) of the integrated circuit, the first output and first input being between the at least one stage and ADC driver of the integrated circuit (see Sakai, [0032], and figure 2). Regarding Claim 6, Sakai as modified by Gagon discloses the amplifier according to claim 5, wherein the first output and first input of the integrated circuit are terminals of the integrated circuit (see Sakai, [0032], and figure 2). Regarding Claim 8, Sakai as modified by Gagon discloses the amplifier according to any one of claim 1, wherein the at least two stages are arranged in use to selectively apply gain to the input signal (e.g. each of AMP1, AMP3 and AMP4 selectively amplify the audio signal). (see Sakai, [0035], and figure 2). Regarding Claim 9, Sakai as modified by Gagon discloses the amplifier according to claim 8, wherein the at least two stages are arranged in use to apply modifiable gain to the input signal (e.g. AMP4 is a variable gain amplifier), (see Sakai, [0049], and figure 2). Regarding Claim 10, Sakai as modified by Gagon discloses the amplifier according to claim 9, wherein the at least two stages include a first stage (e.g. AMP31) and a second stage (e.g. AMP4), (see Sakai, figure 2). Regarding Claim 11, Sakai as modified by Gagon discloses the amplifier according to claim 10, and wherein the first stage and the second stage each have a gain range, the first stage having a different gain range to the second stage (e.g. different gain ranges K1, K3p and K4), (see Sakai, [0042], [0046] and [0047], also figure 2). Regarding Claim 12, Sakai as modified by Gagon discloses the amplifier according to claim 11, wherein the input signal provided to the amplifier passes to the first stage before passing to the second stage (see Gagon, figure 4), the gain range of the first stage being greater than the gain range of the second stage (e.g. the gain of amplifier stage 240 is more than that of the amplifier stage 250, also the gain of the different stages could be set by the user as desired), (see Gagon, column 6 lines 30-43, column 7 lines 1-8). Regarding Claim 13, Sakai as modified by Gagon discloses the amplifier according to claim 11, wherein the gain of the first stage and the gain of the second stage are modifiable in gain steps, the gain steps of the first stage are smaller than the gain steps of the second stage (e.g. the gain of the different stages could be modified by the user as desired), (see Gagon, column 6 lines 37-43). Regarding Claim 21, Sakai as modified by Gagon discloses the amplifier according to claim 1, wherein the plurality of stages are arranged, in use, to maintain input signal provided to the amplifier, when provided as an analogue signal, as an analogue signal (e.g. AMP1 and AMP2 maintained the supplied analogue signal as analogue signal), (see Sakai, [0035]-[0036], and figure 2). Regarding Claim 23, Sakai discloses the amplifier according to claim 1, wherein the plurality of stages include: a plurality of stages (e.g. plurality of amplifiers stages AMP1 to AMP4), at least two of the stages of the plurality of stages being connected in series (e.g. AMP3 and AMP4 are in series), (see figure 2) and each of the at least two stages being a gain stage, the at least two stages being arranged, in use, to apply gain to an input signal provided to the amplifier (e.g. each of the AMP1 to AMP4 is a gain stage for applying gain to an input signal from an audio source 2), a first stage (e.g. AMP1) configured as a preamplifier and arranged in use to receive an input signal and to output an amplified signal (see figure 2); a second stage (e.g. AMP3) configured as an analogue to digital (ADC) drive (e.g. based on output of an ADC 10 and DAC 14) and arranged in use to issue an output signal (e.g. S4), (see figure 2); and an intermediate stage (e.g. AMP2) and connected between an output of the first stage and an input of the second stage (e.g. AMP2 is between AMP1 and AMP3), thereby receiving the amplified signal (see figure 2), wherein the intermediate stage is arranged in use to apply secondary amplification to the amplified signal (e.g. additional amplification is performed by the AMP2) and output a further amplified signal, the second stage being arranged to receive the further amplified signal as an input (see figure 2); and the amplifier further comprises a controller (e.g. DSP 12) arranged in use to select a gain level to be applied by the intermediate stage, thereby modifying a cumulative gain across by the amplifier (e.g. the final gain at the OUT terminal is a cumulative of the gain provided by each of the AMP1 through AMP4). Saiki does not explicitly disclose: each provided by a preamplifier stage, and that the intermediate stage (e.g. AMP2) configured as a preamplifier. However, Gagon in the same field of endeavor teaches an amplifier (e.g. amplifier module 200), (see figure 4), comprising a plurality of stages (e.g. plurality of amplifier stages 237, 240 and 250), at least two of the stages of the plurality of stages being connected in series (see figure 4), and each of the at least two stages being a gain stage, each provided by a preamplifier stage (e.g. each of amplifier stages 237, 240 and 250 is a preamplifier. Also, Gagon teaches an intermediate stage configured as a pre-amplifier (e.g. intermediate stage 240 is also a pre-amplifier), (see Gagon, column 4 lines 12-30, also figures 3 and 4). Therefore, it would have been obvious to any person having an ordinary skill in the art before the effective filing date of the present invention to incorporate providing each of a first stage and a second stage of an amplifier by a preamplifier, and further providing an intermediate stage configured as a pre-amplifier as taught by Gagon in the teachings of Sakai in order to generate additively amplified composite signal with enhanced output features. Regarding Claim 24, Sakai discloses a system for amplifying audio signals (see figure 2), the system comprising: an audio signal input (e.g. IN-terminal); an amplifier according to claim 1, the amplifier comprising a plurality of stages (e.g. plurality of amplifiers stages AMP1 to AMP4), at least two of the stages of the plurality of stages being connected in series (e.g. AMP3 and AMP4 are in series), (see figure 2) and each of the at least two stages being a gain stage, the at least two stages being arranged, in use, to apply gain to an input signal provided to the amplifier (e.g. each of the AMP1 to AMP4 is a gain stage for applying gain to an input signal from an audio source 2), and an output (e.g. OUT-terminal), the plurality of stages being connected between the output and the audio signal input (see figure 2), wherein the at least two stages are arranged, in use, and to apply gain to an input signal provided to the audio signal input; an ADC (e.g. an ADC 10) connected to the output of the amplifier (ADC 10 is connected to the output of AMP1); and an output connected to the ADC and connectable, in use, to an output device (e.g. output device 9); the output being connected to the ADC (e.g. device 9 is connected to ADC 10 via the processing circuit 100), (see Sakai, [0032]-[0035], also figures 1-2). Saiki does not explicitly disclose: each provided by a preamplifier stage. However, Gagon in the same field of endeavor teaches an amplifier (e.g. amplifier module 200), (see figure 4), comprising a plurality of stages (e.g. plurality of amplifier stages 237, 240 and 250), at least two of the stages of the plurality of stages being connected in series (see figure 4), and each of the at least two stages being a gain stage, each provided by a preamplifier stage (e.g. each of amplifier stages 237, 240 and 250 is a preamplifier), (see Gagon, column 4 lines 12-30, also figures 3 and 4). Therefore, it would have been obvious to any person having an ordinary skill in the art before the effective filing date of the present invention to incorporate providing each of a first stage and a second stage of an amplifier by a preamplifier as taught by Gagon in the teachings of Sakai in order to generate additively amplified composite signal with enhanced output features. Regarding Claim 25, Sakai as modified by Gagon discloses the system according to claim 24, further comprising a controller (e.g. an adjustment circuit) connected to the amplifier; the controller arranged, in use based on user input to control the operation of the amplifier (e.g. the gain of the different stages could be modified by the user as desired), (see Gagon, column 6 lines 37-43; column 10 lines 53-61, and figure 7). Allowable Subject Matter Claims 7, 15-16, 18 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record provided on PTO 892 and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OYESOLA C OJO whose telephone number is (571)272-0848. The examiner can normally be reached Monday through Friday 8:00am to 4:00pm Central Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vivian Chin can be reached at 571-272-7840. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OYESOLA C OJO/Primary Examiner, Art Unit 2695
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Prosecution Timeline

Aug 12, 2024
Application Filed
Feb 06, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
93%
With Interview (+11.2%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 715 resolved cases by this examiner. Grant probability derived from career allow rate.

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