Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This is the initial Office Action based on the application filed on August 13, 2024. The Examiner acknowledges the following:
3. Claims 1 – 9 were filed by Applicant.
4. A preliminary amendment was filed to correct the multiple dependence of claims 4, 5 and 9.
5. An amendment was done to the specification paragraph [0065].
6. The drawings filed on 08/13/2024 are accepted by the Examiner.
7. Current claims 1 – 9 are pending and they are being considered for examination.
Information Disclosure Statement
8. The IDS document filed on filed on 08/13/2024 is acknowledged by the Examiner.
Priority
9. Priority data is based on a PCT application PCT/JP2023/006080 filed on 02/20/2023, which refers to a previous Japanese patent application JP-2022-025043, filed on02/21/2022. Certified copies were mailed to the office on 08/13/2024.
Claim Rejections - 35 USC § 102
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Yoshitaka Ozeki et a., WO 2021039161 (A1), hereinafter Ozeki”. (Note: art from the IDS. The translation is provided by the Examiner)
Regarding Claim 1:
Ozeki teaches a detection device comprising: a substrate; a photoelectric conversion element that is provided to the substrate and comprises a semiconductor layer; a transistor that is provided corresponding to the photoelectric conversion element; a first insulating film that is provided on the substrate so as to cover the transistor; and a second insulating film that is provided on the first insulating film so as to cover the photoelectric conversion element and is formed of an organic material, wherein the semiconductor layer of the photoelectric conversion element comprises: a p-type semiconductor layer that is provided on the substrate; an i-type semiconductor layer that is provided on the first insulating film covering the p-type semiconductor layer and is coupled to the p-type semiconductor layer through a contact hole provided in the first insulating film; and an n-type semiconductor layer that is provided on the i-type semiconductor layer, wherein a groove is provided on a side surface of the semiconductor layer, the groove is provided on a side surface of the i-type semiconductor layer near the n-type semiconductor layer and is not provided on the n-type semiconductor layer, and the second insulating film is provided so as to cover the side surface of the semiconductor layer and the groove and, wherein the semiconductor layer of the photoelectric conversion element comprises: an n-type semiconductor layer that is provided on the substrate; an i-type semiconductor layer that is provided on the first insulating film covering the n-type semiconductor layer and is coupled to the n-type semiconductor layer through a contact hole provided in the first insulating film; and a p-type semiconductor layer that is provided on the i-type semiconductor layer. Additionally, the semiconductor layer of the photoelectric conversion element comprises a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer, and the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked in the order as listed, on an electrode provided on the first insulating film, wherein a conductive layer is provided between the first insulating film and the substrate, a contact hole is provided in a region of the first insulating film that is not overlap with the photoelectric conversion element in a plan view, and the electrode is coupled to the conductive layer through the contact hole.
As for Claim 1:
A photodetection device (Fig 3 and Fig 6, detection element 3 or optical sensor having a photoelectric conversion element 30 and Fig 9. See [0020]), comprising: a substrate (substrate 21. See [0078]); a plurality of pixels in rows and columns on the substrate (Fig 2, pixel(s) 3. See [0020; 0050]); a plurality of power lines each located for a corresponding column of the columns of the plurality of pixels (Fig 6, power supply VDD with power signal line SLsf and four signal lines SL. See [0041; 0048]);
a plurality of readout signal lines (Fig 6, readout signal lines SL) each located for a corresponding column of the columns of the plurality of pixels, the plurality of readout signal lines being configured to read voltage signals generated respectively by the plurality of pixels (Fig 6, readout signal lines SL. See [0060; 0069]); and
a plurality of reset signal lines (Fig 6, reset signal lines SLrst. See [0048; 0049; 0051; 0056]) each located for a corresponding row of the rows of the plurality of pixels, each of the plurality of reset signal lines being configured to reset voltage signals (reset control signal RST is applied to the selected scanning lines. See [0025]) from pixels of the plurality of pixels in a corresponding row of the rows (reset control scanning line GLrst, which is connected to a plurality of pixels 3. See [0032; 0033; 0036]), each of the plurality of pixels including a first insulating layer on the substrate (Fig 7, Fig 9, first insulating film 26, second insulating film 27. See [0075; 0076; 0091]),
a photodiode (Fig 6, element or photodiode 30. See [0048]) on a second surface of the first insulating layer (Fig 6, Fig 9, first insulating layer 26. See [0075; 0076; 0091]), the second surface being opposite to a first surface of the first insulating layer facing the substrate, the photodiode including a semiconductor layer (Fig 9, photoconversion element 30B has a semiconductor layer 33, an i-type semiconductor layer 31 and an n-type semiconductor layer 32 stacked in order. See [0089]), an anode electrode (Fig 9, lower electrode or anode electrode 38. See [0090]), and a cathode electrode (Fig 6, upper electrode or cathode electrode 34. Is provided on the photoelectric conversion element 30 and it is connected to a connection wiring 34a indicated by two-dot chain line. See [0059]),
an amplifier transistor (Fig 4 and Fig 6, source follower transistor Msf. It has a semiconductor layer 65, a source electrode 66, a drain electrode 67 and a gate electrode 68. See [0032; 0034; 0037; 0038; 0057]) between the substrate and the first insulating layer, the amplifier transistor including a gate electrode (Fig 6, gate electrode 68. See [0057]) connected to the cathode electrode (Fig 6, upper electrode or cathode electrode 34. Is provided on the photoelectric conversion element 30. See [0059]), an input electrode connected to one power line of the plurality of power lines, and an output electrode connected to one readout signal line of the plurality of readout signal lines (Fig 6, source follower transistor Msf. It has a semiconductor layer 65, a source electrode 66, a drain electrode 67 and a gate electrode 68. See [0057; 0058]),
a reset transistor (Fig 6 and Fig 9, reset transistor Mrst has a semiconductor layer 61, a source electrode 62, a drain electrode 63 and a gate electrode 64. See [0055; 0056]) between the substrate and the first insulating layer, the reset transistor including a gate electrode (Fig 6, gate electrode 64. See [0055; 0056]) connected to one reset signal line of the plurality of reset signal lines, an input electrode connected to the one power line (Fig 6, power supply VDD), and an output electrode connected to the cathode electrode ((Fig 6, upper electrode or cathode electrode 34. Is provided on the photoelectric conversion element 30. See [0059]) and the gate electrode of the amplifier transistor (Fig 6, gate electrode 68. See [0057]), and
a contact hole (Fig 6, contact hole H12 is located between the amplifier and the reset transistor. The lower conductive layer 35 is connected to the reference signal line SLCOM via a contact hole H12. See [0054]) extending through the first insulating layer in a thickness direction and connecting the cathode electrode to the gate electrode of the amplifier transistor and to the output electrode of the reset transistor, the contact hole being located between the amplifier transistor and the reset transistor in a direction in which the one power line extends (Fig 6, contact hole H12 is located between the amplifier and the reset transistor in a first direction Dx. See [0054]).
Regarding Claim 2:
The rejection of claim 1 is incorporated herein. As for claim 2 limitations, Ozeki teaches,
a plurality of select signal lines each located for a corresponding row of the rows of the plurality of pixels, the plurality of select signal lines being configured to set readout periods for the respective voltage signals (Ozeki teaches a scanning driving circuit 15 and a signal line selection circuit 16 as in Fig 1 (See [0017; 0018])are provided in the peripheral area GA, wherein the signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL as seen in Fig 4. The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11 . As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the photoelectric conversion element 30 to the detection unit 40. (See [0026])). The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal line SL As for the select signal lines, Fig 6, select signal lines GLrd (See [0048]). As for the readout periods Ozeki Fig 5 shows a timing chart for operating his device (See [0042 – 0046])).
wherein he plurality of pixels includes a select transistor (Fig 6, select/read transistor Mrd has a semiconductor layer 71, a source electrode 72, a drain electrode 73 and a gate electrode 74. The source follower/amplifier transistor Msf and the select/read transistor Mrd are connected to the output signal line SL (See [0060])).
amplifier transistor (Fig 4 and Fig 6, source follower transistor Msf. It has a semiconductor layer 65, a source electrode 66, a drain electrode 67 and a gate electrode 68. See [0032; 0034; 0037; 0038; 0057])
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over “Yoshitaka Ozeki et a., WO 2021039161 (A1), hereinafter Ozeki” in view of “Hisao Hayashi, US 2002/0056875 A1, hereinafter Hayashi”.
Regarding Claim 7:
The rejection of claim 1 is incorporated herein. Claim 7 includes similar limitations as claim 1. As for the additional limitations of claim 7. Ozeki teaches,
a plurality of select signal lines each located for a corresponding row of the rows of the plurality of pixels, the plurality of select signal lines being configured to set readout periods for the respective voltage signals (Ozeki teaches a scanning driving circuit 15 and a signal line selection circuit 16 as in Fig 1 (See [0017; 0018])are provided in the peripheral area GA, wherein the signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL as seen in Fig 4. The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11 . As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the photoelectric conversion element 30 to the detection unit 40. (See [0026])). The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal line SL
As for the readout periods Ozeki Fig 5 shows a timing chart for operating his device (See [0042 – 0046]).
the select transistor (Ozeki Fig 1, signal line selection circuit 16 corresponds to the selection transistor that selects the pixel lines to be read. See [0026]) “including a channel overlapping the one readout signal line in a plan view”.
Even though, Ozeki teaches most of the limitations of claim 7, it fails to teach or to discuss that the select transistor” including a channel overlapping the one readout signal line in a plan view”, which in the same field of endeavor is taught by Hayashi. Hayashi teaches a display device having a pair of insulating substrates which are connected to each other through a predetermined gap, and electrooptical material held in the gap, comprising: a counter electrode formed in one of said insulating substrates; and a plurality of pixel electrodes and a plurality of thin film transistors which are integrated on the other insulating substrate, wherein each thin film transistor comprises a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, said semiconductor thin film is formed with a channel region confronting said gate electrode, and a source region and a drain region located at both sides of said channel region, and a conductor film is formed on the surface of said interlayer insulating film so as to be overlapped with said channel region.
As for “a transistor including a channel overlapping the one readout signal line in a plan view”, Hayashi shows in Fig 1 that a channel portion 20 and a source/drain electrode 10S (or conductor film 10S) are overlapped (See [0010; 0011]). Fig 3A, 3B shows a similar feature obtained for a thin film transistor 3 (See [0033 – 0037]).
By modifying Ozeki with the features taught by Hayashi using a thin film transistor, it is possible to improve that characteristics of a bottom gate type thin film transistor. (See Hayashi [0002])
Regarding Claim 6:
The rejection of claim 1 is incorporated herein. Ozeki teaches claim 1 limitations. As for the limitations of claim 6. Ozeki teaches,
the amplifier transistor (Fig 4 and Fig 6, source follower transistor Msf. It has a semiconductor layer 65, a source electrode 66, a drain electrode 67 and a gate electrode 68. See [0032; 0034; 0037; 0038; 0057]);
the select transistor (Ozeki Fig 1, signal line selection circuit 16 corresponds to the selection transistor that selects the pixel lines to be read. See [0026]);
the reset transistor (Fig 6 and Fig 9, reset transistor Mrst has a semiconductor layer 61, a source electrode 62, a drain electrode 63 and a gate electrode 64. See [0055; 0056]). However, Ozeki fails to teach
“a channel overlapping the one power/the one readout signal line/at least one of the power line…”, which in the same field of endeavor is taught by Hayashi. Hayashi shows in Fig 1 that a channel portion 20 and a source/drain electrode 10S (or conductor film 10S) are overlapped (See [0010; 0011]). Fig 3A, 3B shows a similar feature obtained for a thin film transistor 3 (See [0033 – 0037]).
By modifying Ozeki with the features taught by Hayashi using a thin film transistor, it is possible to improve that characteristics of a bottom gate type thin film transistor. (See Hayashi [0002])
Regarding Claim 8:
The rejection of claims 1 and 7 is incorporated herein. As for claim 8 limitations, Ozeki teaches a power line (Fig 6, power supply VDD); readout signal lines (Fig 6, readout signal lines SL) having large dimensions in the width or Dx direction of a source/drain part. Hayashi teaches for example the thin film semiconductor device, wherein the thin film (or conductor film) has a width dimension larger than that of the channel region (See [0014; 0022]).
Therefore, in the combination of Ozeki and Hayashi, nothing precludes to make some of the layers larger that others or the size of the components larger.
Regarding Claim 9:
Then rejection of claim 7 is incorporated herein. As for claim 9 limitations, Hayashi teaches as for Fig 1, the use of some metal like aluminum used for the wirings like the conductor films 10D and 10S which are formed in the interlayer insulating film 9 (See [0007; 0008]).
Claims 3 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over “Yoshitaka Ozeki et a., WO 2021039161 (A1), hereinafter Ozeki” in view of “Eiji Kanda et al., US 2008/0315068 A1, hereinafter Kanda”. (Note: both are art from the IDS. The WO art has the translation provided by the Examiner)
Regarding Claim 3:
The rejection of claim 1 is incorporated herein. Ozeki teaches claim 1 limitations; however, it does not teach the limitations of claim 3, which in the same field of endeavor is taught by Kanda. Kanda teaches a photoelectric converter having a semiconductor layer comprising in one pixel: a photoelectric conversion element, a reading field-effect transistor having a gate for receiving signal charges generated in the photoelectric conversion element and a source and a drain for reading a signal corresponding to the signal charges accumulated in the gate, selection-switch means set between the reading field-effect transistor and a power supply, and reset means for resetting the gate; wherein the photoelectric conversion element, the reading field-effect transistor, the selection-switch means, and the reset means are formed on a common insulating support body. As for claim 3 limitations Kanda Fig 16, Fig 19 show that a photodiode 47 is formed to overlap an amplifier transistor 48, a reset transistor 41, the first capacitive element 43, the contact hole 79b in a plan view (See [0118; 0121]).
By modifying Ozeki with the features of Kanda, it is possible to improve the resolution of the detection device (See Kanda [0021; 0102]).
Regarding Claim 4:
The rejection of claim 1 is incorporated herein. Kanda Fig 16 and Fig 19 teach a transparent anode electrode 47 made of Indium Tin Oxide (ITO) and a cathode electrode 43a made of Al – Nd or the like (See [0118; 0121]).
By modifying Ozeki by adding the features as taught by Kanda, it is possible to improve the resolution of the detection device (See [0021]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over “Yoshitaka Ozeki et a., WO 2021039161 (A1), hereinafter Ozeki” in view of “Isao Kobayashi et al., US 2002/0056810 A1, hereinafter Kobayashi”. (Note: both are art from the IDS. The WO art has the translation provided by the Examiner)
Regarding Claim 5:
The rejection of claim 1 is incorporated herein. Ozeki teaches claim 1 and also as seen in Fig 6, a first insulating film/layer 26 and a second insulating film/layer 27 as to cover the photoelectric conversion elements 30 (See [0073; 0075]). Additionally, Ozeki teaches as for the modification done to Fig 4, the reference potential VCOM is supplied to the n-type semiconductor layer 32. In this case the reference potential VCOM has a potential higher than the reset potential Vrst so that the photoelectric conversion element 30A is reverse bias driven (See [0087]). However, it does not teach or suggest the other limitations of claim 5, which in the same field of endeavor is taught by Kobayashi. Kobayashi teaches a photoelectric converter having a semiconductor layer comprising in one pixel: a photoelectric conversion element, a reading field-effect transistor having a gate for receiving signal charges generated in the photoelectric conversion element and a source and a drain for reading a signal corresponding to the signal charges accumulated in the gate, selection-switch means set between the reading field-effect transistor and a power supply, and reset means for resetting the gate; wherein the photoelectric conversion element, the reading field-effect transistor, the selection-switch means, and the reset means are formed on a common insulating support body. As for claim 5 limitations, Kobayashi teaches in Fig 7, a photoelectric conversion layer with a PIN-type photodiode sensor with an ITO 710; a second insulating layer 711 that covers the photodiode layer; a first Al layer 712 (or bias line) and a second contact hole 712 (at bottom), which does not overlap a first contact hole 715 (at top). (See [0060; 0061; 0062]).
By modifying Ozeki with the circuit of Kobayashi, which allows for a compact circuit layout because the power supply line and reset power supply line of the source follower/amplifier are used in common (See Kobayashi [0046]).
Contact
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARLY S.B. CAMARGO whose telephone number is (571)270-3729. The examiner can normally be reached on M-F 8:00-5:00 PM.
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/MARLY S CAMARGO/Primary Examiner, Art Unit 2638