DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagaune (US 2014/0048918).
Regarding Claim 1, Nagaune discloses a power module (power semiconductor module [0002] Fig 8A/B), comprising:
a semiconductor element (semiconductor chip [0003] Fig 8A/B);
an insulating substrate (conductor pattern 2a, insulating substrate 1, conductor pattern 2b [0003] Fig 8A/B) including a mounting surface on which the semiconductor element (semiconductor chip 3 [0003] Fig 8A/B) is mounted; and
a heat radiation member (heat dissipating base member 4 [0003] Fig 8A/B) bonded to a surface of the insulating substrate (2a, 1, 2b Fig 8A/B) on a side opposite to the mounting surface,
wherein a bonding region (shown in annotated Fig 8A) in the insulating substrate (2a, 1, 2b Fig 8A/B) bonded to the heat radiation member (4 Fig 8A/B) is a region corresponding to a portion on which the semiconductor element (3 Fig 8A/B) is mounted, and
an area of the bonding region (shown in annotated Fig 8A) in the insulating substrate (2a, 1, 2b Fig 8A/B) bonded to the heat radiation member (4 Fig 8A/B) is smaller than an area of the portion on which the semiconductor element (3 Fig 8A/B) is mounted.
PNG
media_image1.png
848
1227
media_image1.png
Greyscale
Regarding Claim 3, Nagaune discloses the limitations of claim 1 as explained above. Nagaune further discloses
wherein the insulating substrate (2a, 1, 2b Fig 8A/B) includes a conductive layer (conductor pattern 2a [0003] Fig 8A/B) forming a surface on a side opposite to the mounting surface, and the conductive layer (conductor pattern 2a [0003] Fig 8A/B) is formed in a region corresponding to a portion on which the semiconductor element (3 Fig 8A/B) is mounted.
Regarding Claim 5, Nagaune discloses the limitations of claim 1 as explained above. Nagaune further discloses
wherein the insulating substrate (2a, 1, 2b Fig 8A/B) includes a conductive layer (conductor pattern 2a [0003] Fig 8A/B) forming a surface on a side opposite to the mounting surface, and the conductive layer (conductor pattern 2a [0003] Fig 8A/B) is divided into the region corresponding to the portion on which the semiconductor element (3 Fig 8A/B) is mounted and another region by a slit (shown in annotated Fig 8A/B).
PNG
media_image2.png
474
724
media_image2.png
Greyscale
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori et al (US 2010/0193941) (the examiner notes that claim 1 is rejected with Mori et al in order to reject dependent claim 6).
Regarding Claim 1, Mori et al discloses a power module (power module [0017] Fig 1), comprising:
a semiconductor element (semiconductor chip 20 [0018] Fig 1);
an insulating substrate (insulating substrate 10 [0018] Fig 1) including a mounting surface on which the semiconductor element (20 Fig 1) is mounted; and
a heat radiation member (heat sink 30 [0018] Fig 1) bonded to a surface of the insulating substrate (10 Fig 1) on a side opposite to the mounting surface,
wherein a bonding region in the insulating substrate (10 Fig 1) bonded to the heat radiation member (30 Fig 1) is a region corresponding to a portion on which the semiconductor element (20 Fig 1) is mounted, and
an area of the bonding region in the insulating substrate (area of coating layer 13 [0019] Fig 1) bonded to the heat radiation member (30 Fig 1) is smaller than an area of the portion (insulating ceramic substrate 11 [0019] Fig 1) on which the semiconductor element (20 Fig 1) is mounted.
Regarding Claim 6, Mori et al discloses the limitations of claim 1 as explained above. Mori et al further discloses
wherein provided to the heat radiation member (30 Fig 1) is a convex part (top sheet 40 [0026] Fig 1) having contact with a region in which the heat radiation member (30 Fig 1) is not bonded in the surface of the insulating substrate (10 Fig 1) on the side opposite to the mounting surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaune (US 2014/0048918) in view of Katsuyama et al (US 2009/0051307).
Regarding Claim 2, Nagaune discloses the limitation of claim 1 as explained above. Nagaune does not disclose
wherein the insulating substrate includes a plurality of insulating substrates, the semiconductor element includes a plurality of semiconductor elements, the plurality of semiconductor elements are six groups of transistors and diodes, and
two or three groups of transistors and diodes in the six groups of transistors and diodes are mounted on each of the insulating substrates.
Katsuyama et al, in the related art of semiconductor devices that include power modules, discloses
the semiconductor element (semiconductor elements 4/IGBTs and diodes 5 [0011] Fig 1) includes a plurality of semiconductor elements (IGBTs 4 and diodes 5 Fig 1), the plurality of semiconductor elements (IGBTs 4 and diodes 5 Fig 1) are six groups of transistors (IGBTs 4 Fig 1) and diodes (diodes 5 Fig 1), and
two or three groups of transistors (IGBTs 4/temperature sensor 22 [0004] Fig 10) and diodes (diode chip 21 [0004] Fig 10) in the six groups of transistors and diodes (shown in Fig 10) are mounted on an insulating substrate (insulating substrate 20 [0003] Fig 10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaune to include wherein the insulating substrate includes a plurality of insulating substrates, the semiconductor element includes a plurality of semiconductor elements, the plurality of semiconductor elements are six groups of transistors and diodes as taught by Katsuyama et al in order to expand the electrical functioning capability of the devices, i.e. more semiconductor elements. Further, a person of ordinary skill in the art would have recognized that having multiple insulating substrates would be advantageous in protecting the device to prevent breakdown due to overheating [0003] (see MPEP 2143.I(D)).
The combination of Nagaune and Katsuyama et al now discloses
wherein the insulating substrate (conductor pattern 2a, insulating substrate 1, conductor pattern 2b [0003] Fig 8A/B Nagaune) includes a plurality of insulating substrates (20 Fig 10 Katsuyama et al);
two or three groups of transistors and diodes (IGBTs 4 and diodes 5 Fig 1/(IGBTs 4/temperature sensor 22 Fig 10 Katsuyama et al)) in the six groups of transistors and diodes are mounted on each of the insulating substrates (2a, 1, 2b Fig 8A/B Nagaune/20 Fig 10 Katsuyama et al).
Regarding Claim 7, Nagaune discloses the limitations of claim 1 as explained above. Nagaune does not directly disclose
a main conversion circuit including the power module according toa main conversion circuit including the power module according to converting an electrical power which has been inputted, and outputting the electrical power; and
a control circuit outputting a control signal for controlling the main conversion circuit to the main conversion circuit.
Katsuyama et al, in the related art of semiconductor devices that include power modules, discloses
a main conversion circuit (directed current power source 2, comparing section 12, junction temperature calculation section 11, temperature detection section 10, and electric current detection section 9 [0011]-[0012] Fig 1) including the power module (intelligent power module IPM [0003]) according to a main conversion circuit (circuit including 2, 9-11, and IPM shown in Fig 1) including the power module (IPM) according to converting an electrical power which has been inputted, and outputting the electrical power [0011]; and
a control circuit (driving control section 7 [0011] Fig 1) outputting (shown in Fig 1) a control signal for controlling the main conversion circuit (circuit including 2, 9-11, and IPM shown in Fig 1) to the main conversion circuit (circuit including 2, 9-11, and IPM shown in Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaune to include a main conversion circuit and a control circuit as taught by Katsuyama et al in order to control the electrical functioning of the device that includes a temperature protecting function [0003]. Further, a person of ordinary skill in the art would have recognized that controlling the operation of the semiconductor elements would help optimize the electrical functioning capability of the device while minimizing damage from excessive temperature [0009]-[0010] (see MPEP 2143.I(D)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nagaune (US 2014/0048918) in view of Yuki et al (US 2023/0298961).
Regarding Claim 4, Nagaune discloses the limitations of claim 1 as explained above. Nagaune further discloses
wherein the insulating substrate (conductor pattern 2a, insulating substrate 1, conductor pattern 2b [0003] Fig 8A/B) includes a conductive layer (conductive pattern 2a [0003] Fig 8A/B) forming a surface on a side opposite to the mounting surface, and
Nagaune does not disclose
a solder resist is formed in a region other than the region corresponding to the portion on which the semiconductor element is mounted in the conductive layer so as not to be bonded to the heat radiation member.
Yuki et al, in the related art of semiconductor devices that include power modules, discloses
a solder resist (solder resist portion 20 [0037] Fig 1-3) is formed in a region other than the region corresponding to the portion on which the semiconductor element (semiconductor chip is soldered to circuit-side metal plate 11 [0032] Fig 3) is mounted in the conductive layer (circuit-side metal plate 11 [0032] Fig 3) so as not to be bonded to the heat radiation member (heat sink plate 30 [0040] Fig 3).
It would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaune to include a solder resist as taught by Yuki et al in order to prevent wetting and spreading of the solder [0043]. Further, a person of ordinary skill in the art would have recognized that preventing wetting and spreading of the solder would be advantageous in having a stronger and more functional bond which would optimize electrical function while providing structural stability (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. FIllion et al (US 2007/0040186) which discloses a power semiconductor chip [0010], and Yuasa et al (US 2019/0115228) which discloses a circuit substrate for a power module [0016].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights