Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Specifically, claim 17 recites a micro semiconductor LED structure comprising “a first edge layer of the first conductivity type” and “a second edge layer of the second conductivity type,” wherein the claim explicitly defines that the first and second conductivity types “have opposite doping.” However, the final limitation of the claim requires that “the first and the second edge layer are intentionally undoped.”
An analysis of the factors set forth in In re Wands, 858 F.2d 731, 8 USPQ2d 1400 (Fed. Cir. 1988), demonstrates that a person having ordinary skill in the art (PHOSITA) would not be able to make and use the claimed invention without undue experimentation:
(A) The breadth of the claims: The claim is directed to a specific structural arrangement of a micro LED, but encompasses a physical impossibility within the first and second edge layers—requiring them to simultaneously possess a conductivity type defined by “doping” while also being “intentionally undoped.”
(B) The nature of the invention: The invention relates to semiconductor physics, specifically the epitaxial growth and doping profiles of micro LED structures.
(C) The state of the prior art: In the semiconductor arts, it is a well-established physical principle that a semiconductor layer is either doped with impurities to achieve a specific conductivity type (e.g., n-type or p-type), or it is intentionally left undoped (i.e., an intrinsic or i-type layer).
(D) The level of one of ordinary skill: The level of ordinary skill in the art is high. A PHOSITA possesses a strong understanding of semiconductor physics, doping mechanisms, and material properties. Such a person would recognize that a single layer cannot simultaneously be intentionally doped and intentionally undoped.
(E) The level of predictability in the art: The physical properties of doped versus undoped semiconductors are highly predictable. It is predictably impossible to manufacture a semiconductor layer that satisfies both of these mutually exclusive conditions at the same time.
(F) The amount of direction provided by the inventor: The specification provides no direction or guidance on how to manufacture a single semiconductor layer that is simultaneously doped and intentionally undoped. To the contrary, the specification (page 2, lines 19-29) explicitly presents these two states as mutually exclusive alternatives, stating the layers may be doped, or “Alternatively, for example, the first and the second edge layers may be intentionally left undoped.”
(G) The existence of working examples: There are no working examples in the specification demonstrating a layer that is both doped to a conductivity type and intentionally undoped.
(H) The quantity of experimentation needed to make or use the invention: Because the claimed structure requires a physical impossibility (a layer that is both doped and undoped), the amount of experimentation required to make the claimed invention would be infinite. Any required experimentation that is physically impossible to successfully complete is, by definition, undue.
Conclusion: Weighing all the Wands factors, the specification, at the time the application was filed, would not have taught one skilled in the art how to make and/or use the full scope of the claimed invention without undue experimentation. Because it is physically impossible to make a layer that is simultaneously doped and intentionally undoped, the claim is not enabled.
(Examiner’s Note: As noted in the accompanying 35 U.S.C. 112(b) rejection, it appears the applicant has inadvertently combined two mutually exclusive alternative embodiments from page 2 of the specification into a single claim. Amending the claim to select one of these mutually exclusive alternatives will overcome this rejection).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, the claim is internally inconsistent. The claim recites “a first edge layer of the first conductivity type… and a second edge layer of the second conductivity type” and further defines that the first and second conductivity types “have opposite doping.” However, the claim subsequently recites that “the first and the second edge layer are intentionally undoped.” A layer cannot simultaneously have a conductivity type defined by “doping” and be “intentionally undoped.” It is unclear whether the edge layers are doped to achieve a conductivity type or if they are intrinsic (undoped).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Kawasumi et al. (US 5732099 A), hereinafter “Kawasumi” in view of Xue-Lun Wang (US 20070200135 A1), hereinafter “Wang”.
Regarding claim 33: Kawasumi discloses a micro semiconductor LED structure comprising:
a first semiconductor layer (see, for example, fig. 2, element 1, col. 2, line 12) of a first conductivity type (fig. 2, element 1, col. 2, line 12);
a second semiconductor layer (see, for example, fig. 2, element 2, col. 2, line 13) of a second conductivity type (fig. 2, element 2, col. 2, line 13), which is arranged on the first semiconductor layer;
an active layer sequence (fig. 2, elements 4-8, col. 2, lines 15-21) comprising a first edge layer (fig. 2, element 4, col. 2, lines 15-16) of the first conductivity type (fig. 2, element 4, col. 2, lines 15-16) facing the first semiconductor layer and a second edge layer (fig. 2, element 8, col. 2, lines 20-21) of the second conductivity type (fig. 2, element 8, col. 2, lines 20-21) facing away from the first semiconductor layer; and
a third semiconductor layer (fig. 2, element 9, col. 2, lines 21-22) of the second conductivity type (fig. 2, element 9, col. 2, lines 21-22 ), which is arranged at least on the active layer sequence,
wherein the first conductivity type (fig. 2, element 1 , col. 2, line 12) and the second conductivity type (fig. 2, element 2, col. 2, line 13) have opposite doping (fig. 2, elements 1 and 2, col. 2, lines 59-60),
wherein the second semiconductor layer (fig. 2, element 2, col. 2, line 13) has at least one window (see annotated fig. 4) which penetrates through the second semiconductor layer from a side of the second semiconductor layer facing away from the first semiconductor layer (see, for example, fig. 2, element 1, col. 2, line 12) toward the first semiconductor layer,
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wherein the first semiconductor layer has a recess (see, for example, fig. 2 below) in a region of the window (see, for example fig. 4, above),
wherein the active layer sequence is arranged at least in the recess (see, for example, fig. 2 below),
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wherein the first edge layer (see, fig. 2, element 4, page 12, col 2, lines 15-16) in the recess is electrically conductively connected to the first semiconductor layer (see, fig. 2, element 1, col. 2, line 12),
wherein the third semiconductor layer (see, fig. 2, element 9, col. 2, lines 21-22) is arranged on the active layer sequence (see, fig. 2, elements 4-8, col. 2, lines 15-21 ) at least in the region of the window,
wherein the second edge layer (see, fig. 2, elements 8, col. 2, lines 20-21) is electrically conductively connected to the third semiconductor layer (see, fig. 2, element 9, col. 2, lines 21-22),
wherein the first semiconductor layer and the second semiconductor layer form a pn- junction (horizontal interface between 1(n) and 2(p)) and the active layer sequence penetrates the pn-junction (fig 2):
Kawasumi does not teach wherein the micro semiconductor LED structure does not include a growth substrate.
However, Wang discloses wherein the micro semiconductor LED structure does not include a growth substrate (see, for example, fig. 2, para [0041]) in order to sweep it away from the path of the radiation of the light.
It would have been obvious to a person of ordinary skill before the effective filing date of the claimed invention, to modify Kawasumi with the teachings of Wang, to remove a growth substrate from the micro semiconductor LED structure to enable light radiation and to avoid absorption or scattering of light of the LED in order to improve light extraction efficiency and reduce costs (grinding, dicing, and packaging) (Wang, para [0041]).
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Ota (US 11133431 B2) discloses flanks of the recess and the window of the micro semiconductor LED structure extend substantially perpendicular to a main extension plane of the first semiconductor layer (see fig. 5C).
Sasaki (US 5404031 A) discloses the thickness of the active layer sequence in a region of the flanks of the micro semiconductor LED structure is smaller than a thickness of the active layer sequence in a region along the bottom surface of the recess (fig. 1A, element13, col. 2, lines 46-49). Sasaki further discloses that the window and the recess are produced by photolithography followed by etching (figs. 2A, col. 2, lines 6-14).
Chen (US 20040089861 A1) discloses the method of removing the third semiconductor and the active layer sequence (see fig. 2A, para [0026]) to such an extent that the second semiconductor layer is freed from the active layer sequence next to the window.
Any inquiry concerning this communication from the examiner should be directed to Berhanu G Demissie whose telephone number is (571)270-0898). The examiner can normally be reached M -F 8:00 - 5:00.
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/BERHANU GELETA DEMISSIE/Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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