DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The amendment filed on 8/14/2024 has been entered. In the amendment, Applicant amended claims 3, 7, 9-11, 16, 19, 21, 23, 25, 28 and 30, cancelled claims 4, 12-13, 15, 18, 20, 22, 26-27 and 29. Currently claims 1-3, 5-11, 14, 16-17, 19, 21, 23-25, 28 and 30 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-11, 14, 16-17, 19, 21, 23-25, 28 and 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the element “the latch signal terminal” in ll. 7 from the bottom. There is insufficient antecedent basis for this limitation in the claim. Furthermore, claim 1 recites the element “a first mode of a previous stage of shift register” in ll. 4-5 from the bottom. It is unclear whether or not it is related to the limitation “wherein … at least one stage of shift register comprises a shift sub-circuit and an output sub-circuit, wherein the shift sub-circuit is provided with a first node” recited in ll. 1-5 of the instant claim. If there is a relationship between the two, “a first mode of a previous stage of shift register” is suggested changed to “the respective first mode of a previous stage of shift register”.
Claims 2-3, 5-11, 14, 16-17, 19, 21, 23-25, 28 and 30 are rejected because they depend on claim 1.
Claim 10 is further rejected because it recites “(n+1)-st stage of shift register”, which includes (N+1)-st stage that is out of the range of a total number of N stages of shift register. Claims 11, 14, 16-17, 19, 21, 23-25, 28 and 30 are further rejected because they depend on claim 10.
Claim 28 is further rejected because it recites the “the base substrate” in ll. 3. There is an insufficient basis for this element in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (US 2022/0076618).
Regarding claim 1, Lai teaches a display substrate (Fig. 1: inherent substrate of display panel illustrated) having a display area (Fig. 1: display region AA) and a non-display area (Fig. 1: non-display region of display panel accommodating driving circuit 100), wherein the display area is provided with a pixel drive circuit (Fig. 1: pixel circuit 400 in one display unit 300), and the non-display area is provided with a gate drive circuit (Figs. 1-2: driving circuit 100), the gate drive circuit comprises a plurality of shift registers (Fig. 2: N cascaded shift registers 200, i.e., ASG1 to ASGN) which are cascaded, at least one stage of shift register comprises a shift sub-circuit (Figs. 4 and 6: first control part 10) and an output sub-circuit (Figs. 4 and 6: second control part 20), wherein the shift sub-circuit is provided with a first node (Figs. 4 and 6: node N1 or N2);
the shift sub-circuit is connected with a signal input terminal (Figs. 4 and 6: terminal for receiving an input signal IN), a first clock signal terminal (Figs. 4 and 6: terminal for receiving first clock signal CK), a second clock signal terminal (Figs. 4 and 6: terminal for receiving second clock signal XCK), a first power supply terminal (Figs. 4 and 6: first voltage signal VGH1), a second power supply terminal (Figs. 4 and 6: second voltage signal VGL1) and a cascaded signal output terminal (Figs. 4 and 6: output terminal associated with third node N3 that outputs signal “Next”) respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the cascaded signal output terminal under control of signals of the signal input terminal, the first clock signal terminal and the second clock signal terminal (Fig. 6: signal “Next” is output as a signal of “VGH1” or “VGL1” under cooperative control of signal “IN”, signal of “CK” and signal of “XCK”);
the output sub-circuit is connected with a control signal terminal (Figs. 4 and 6: terminal for receiving frequency control signal CRL), a third power supply terminal (Figs. 4 and 6: fifth voltage signal VGH3), a fourth power supply terminal (Figs. 4 and 6: sixth voltage signal VGL3), the cascaded signal output terminal and a drive signal output terminal (Figs. 4 and 6: terminal for outputting output signal OUT) respectively, and is configured to provide a signal of the third power supply terminal or the fourth power supply terminal to the drive signal output terminal under control of signals of the latch signal terminal, the control signal terminal and the cascaded signal output terminal (Fig. 6: signal “OUT” is output as a signal of VGH3 or a signal of VGL3 under control of latch signal CRL, control signal CRL and cascaded signal Next); and
the control signal terminal is connected with a first node of a previous stage of shift register with respect to a current stage of shift register (Fig. 2: CRL terminal of a current stage shift register ASG2 is indirectly connected with a node of previous stage ASG1 via first frequency control signal line X1CRL), the drive signal output terminal is connected with the pixel drive circuit (Figs. 1-2), and the cascaded signal output terminal is connected with a signal input terminal of at least one stage of shift register other than the current stage of shift register (Fig. 2: “Next” signal terminal of current stage shift register ASG2 is connected with “IN” signal terminal of next stage shift register ASG3).
Regarding claim 2, Lai teaches the display substrate of claim 1, wherein the shift sub-circuit comprises at least a sixth transistor (Fig. 6: M13), a seventh transistor (Fig. 6: M15), a ninth transistor (Fig. 6: M17), and a tenth transistor (Fig. 6: M18); and
the first node is connected with the sixth transistor and the seventh transistor respectively (Fig. 6: node N2 is connected with M13 and M15), the ninth transistor is connected with the first power supply terminal and the cascaded signal output terminal respectively (Fig. 6: M17 is connected with VGH1 terminal and “Next” terminal), and the tenth transistor is connected with the second power supply terminal and the cascaded signal output terminal respectively (Fig. 6: M18 is connected with VGL1 terminal and “Next” terminal).
Regarding claim 3, Lai teaches the display substrate of claim 1, wherein the shift sub-circuit comprises a fourth capacitor (Fig. 6: C1);
a first plate of the fourth capacitor is connected with the second power supply terminal (Fig. 6: lower terminal of C1 is connected with VGL1 terminal), and a second plate of the fourth capacitor is connected with the cascaded signal output terminal (Fig. 6: upper terminal of C1 is connected with “Next” terminal);
(the range is not realistic when used for a display panel); or
wherein the output sub-circuit comprises at least a nineteenth transistor (Fig. 6: M3), a twentieth transistor (Fig. 6: M2), a twenty-fourth transistor (Fig. 6: M1), a twenty-fifth transistor (Fig. 6: M5), and a twenty-sixth transistor (Fig. 6: M6);
the nineteenth transistor is connected with the latch signal terminal (Fig. 6: M3 is connected with CRL terminal), the twentieth transistor is connected with the cascade signal output terminal (Fig. 6: M2 is connected with “Next” terminal via M1), the twenty-fourth transistor is connected with the third power supply terminal (Fig. 6: M1 is connected with VGH2 via C1), the twenty-fifth transistor is connected with the third power supply terminal and the drive signal output terminal respectively (Fig. 6: M5 is connected with VGH2 terminal and “OUT” terminal), and the twenty-sixth transistor is connected with the fourth power supply terminal and the drive signal output terminal respectively (Fig. 6: M6 is connected with VGL2 terminal and “OUT” terminal).
Regarding claim 5, Lai teaches the display substrate of claim 1, wherein the shift sub-circuit is further provided with a fifth node (Fig. 6: node N3), the shift sub-circuit further comprises a fourth transistor (Fig. 6: M14) and a fifth transistor (Fig. 6: M11), the fifth node is connected with the fourth transistor and the fifth transistor respectively (Fig. 6: node N3 is connected with M14 and M11 via VGL1 terminal); and
the output sub-circuit is further connected with the fifth node and the fourth power supply terminal respectively (Fig. 6: second control part 20 is connected with node N3 and VGL1 terminal).
Regarding claim 6, Lai teaches the display substrate of claim 5, wherein the output sub-circuit comprises at least a nineteenth transistor (Fig. 6: M3), a twentieth transistor (Fig. 6: M2), a twenty-fourth transistor (Fig. 6: M1), a twenty-fifth transistor (Fig. 6: M5), and a twenty-sixth transistor (Fig. 6: M6);
the nineteenth transistor is connected with the latch signal terminal (Fig. 6: M3 is connected with CRL terminal), the twentieth transistor is connected with the cascade signal output terminal (Fig. 6: M2 is connected with “Next” terminal via M1), the twenty-fourth transistor is connected with the third power supply terminal (Fig. 6: M1 is connected with VGH2 via C1), the twenty-fifth transistor is connected with the third power supply terminal and the drive signal output terminal respectively (Fig. 6: M5 is connected with VGH2 terminal and “OUT” terminal), and the twenty-sixth transistor is connected with the fourth power supply terminal and the drive signal output terminal respectively (Fig. 6: M6 is connected with VGL2 terminal and “OUT” terminal).
Regarding claim 30, further Lai teaches a display apparatus (Fig. 1), comprising the display substrate according to claim 1.
Allowable Subject Matter
Claims 7-11, 14, 16-17, 19, 21, 23-25 and 28 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner' s statement of reasons for allowance:
Claim 7: the lengths of active patterns of recited transistors in the first direction and the second direction are specifically related as recited.
Claim 9: the recited four conductive layers are used to specifically accommodate recited electrodes and plates of respective transistors and capacitors.
Claim 28: the specific arrangement of the output sub-circuit related to the sub-circuit on the base substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0075599 discloses related technique with less complexity.
US 2022/0076611 teaches claim 1 in the similar manner as does the cited reference above
US 2019/0325800 discloses related technique with less complexity.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629
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