DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim(s) 1-4, 13-14, 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pyon (KR 20190040160 A) in view of Ha (US 20020036724) and further in view of Ishi (US 20130314574 A1).
Regarding claim 1:
discloses a display substrate (see Fig. 35B), comprising:
a base substrate (110. Fig. 19), provided with a plurality of pixels with pixels array (pixels in display panel), wherein each pixel of at least part of the plurality of pixels comprises a plurality of sub-pixels (The organic light emitting display includes a plurality of pixels including an organic light emitting diode (OLED), and each pixel includes a plurality of thin film transistors and capacitors for driving the organic light emitting diodes. The plurality of thin film transistors basically include a switching thin film transistor and a driving thin film transistor see pg. ), each sub-pixel of at least part of the plurality of sub-pixels comprises a pixel circuit (Fig. 15), the pixel circuit comprises:
a light-emitting device (OLED), a storage capacitor (cst),
a driving transistor (T1) and a data writing transistor (T2), wherein each of the driving transistor and the data writing transistor comprises an active layer (semiconductor layer), a gate electrode, a first electrode and a second electrode, the driving transistor is configured to control the light-emitting device to emit light (see Fig. 15, pg 18-20);
a data line (Dm), connected (electrically connected with connected by D3) with the first electrode of the data writing transistor (T2) and configured to provide a data signal to the data writing transistor (see Fig. 2, Pg 2-4), wherein the data writing transistor is configured to write the data signal to the gate electrode of the driving transistor (T1) in response to a first scan signal (Sn-1) applied to the gate electrode of the data writing transistor (T4) (see Pg. 38-40 of pg. 504) ; and
a first connection structure (178, which Fig. 15, 17), connected (electrically connected) with the gate electrode of the driving transistor (T1) and a first electrode plate (cst1) of the storage capacitor (Cst) (see Fig. 15, The storage capacitor Cst includes a gate electrode 125a of the thin film transistor T1, a second electrode 175 of the storage capacitor Cst, and an interlayer insulating film 160 therebetween. Also see Fig. 17), wherein both the data line (Dm or 171, see Fig.17 and the first connection structure (178) extend along a first direction , and the data line comprises an overlapping part (overlap at T2, see Fig. 17, the first connection structure (178) is at least partially opposite to the overlapping part of the data line (Dm) in a second direction (direction at 177) (see Fig. 10, 11), and the second direction is parallel to the base substrate (110) and perpendicular to the first direction (see Fig. 3); the first connection structure and the overlapping part of the data line respectively constitute a first electrode plate and a second electrode plate of a parasitic capacitance (i.e. parasitic capacitance exist between TFT and pixel electrodes) (see Pg.18-20, 26-27).
However, Pyon does not specifically disclose the first connection structure and the overlapping part of the data line are insulated from each other and
a ratio of a capacitance value of the parasitic capacitance to a capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.
Ha discloses the first connection structure and the overlapping part of the data line are insulated from each other (a fourth insulating film is formed on the data line and the connection electrode and patterned to expose the connection electrode Pg 19 of 53).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Long with the teaching of Ha, thereby providing high performance display device.
Ishi (US 20130314574 A1) discloses plurality of pixels arranged in an array (see Fig. 5A, [0196]) and a ratio of a capacitance value of the parasitic capacitance (Ci) to a capacitance value of the storage capacitor (Cp). The limitations “a ratio of a capacitance value of the parasitic capacitance to a capacitance value of the storage capacitor is greater than 0.001 and less than 0.01” obvious in the system of Ishi. Since Ishi in [0085] discloses parasitic capacitance Ci storage capacitor Cp exists between the storage capacitor 907 of adjacent pixels. To suppresst he interference level, the effect the ratio of Cp to Ci needs to be increased). In accordance with optimizing pixel charecteristic, it is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005). However, if the reference’s disclosed range is so broad as to encompass a very large number of possible distinct compositions, this might present a situation analogous to the obviousness of a species when the prior art broadly discloses a genus. Id. See also In re Baird, 16 F.3d 380, 29 USPQ2d 1550 (Fed. Cir. 1994); In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992); MPEP § 2144.08.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pyon with the teaching of Ha, and Ishi, thereby providing high efficient data transmission in the display device.
Regarding claim 2:
Pyon in view of Ha and Ishi discloses wherein a size of one of the sub-pixels in the second direction is greater than 50 μm (see Ishi [0094]), and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is less than 0.005 (see Ishi , [0085], see the discussion in claim 1). Same motivation as applied to claim 1.
Regarding claim 3:
Pyon in view of Ha and Ishi discloses wherein a size of one of the sub-pixels in the second direction is less than is less than or equal to 68 μm (see Ishi [0094]),
and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than or equal to 0.003 (see Ishi , [0085], see the discussion in claim 1). Same motivation as applied to claim 1.
Regarding claim 4:
Pyon in view of Ha and Ishi discloses wherein a size of one of the sub-pixels in the second direction is less than is less than or equal to 50 μm (see Ishi [0094]);
and the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.005 and less than 0.006 ((see Ishi , [0085], see the discussion in claim 1). Same motivation as applied to claim 1.
Regarding claim 41:
Pyon discloses a display apparatus, comprising the display substrate according to claim 1 (see Fig.15, (see Pg.18-20, 21-24).
Regarding claim 13:
Pyon discloses wherein at least one of the overlapping part of the data line and the first connection structure comprises a recessed part (BP ), the recessed part of any one of the overlapping part of the data line and the first connection structure is recessed in a direction away from other one of the overlapping part of the data line and the first connection structure in the second direction (see Fig. 17pg, 21-24).
Regarding claim 14:
Pyon discloses wherein the overlapping part of the data line (Dm) comprises a first recessed part (Dm recessed in a space ), the first recessed part is recessed in a direction away from the first connection structure (178) in the second direction, and a part of the first connection structure opposite to the data line is in a straight strip shape (see Fig. 17); or, the first connection structure comprises a second recessed part, the second recessed part is recessed in a direction away from the overlapping part of the data line in the second direction, and the overlapping part of the data line is in a straight strip shape; or, the overlapping part of the data line comprises a first recessed part, the first recessed part is recessed in a direction away from the first connection structure in the second direction, and the first connection structure comprises a second recessed part, the second recessed part is recessed in a direction away from the overlapping part of the data line in the second direction (see Fig. 17, page 21-24).
Allowable Subject Matter
2. Claim 5-12, 17, 19, 20-21, 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for allowance:
Regarding claim 5:
The closest art of record singly or in combination fails to teach or suggest the limitations “an edge of the first part of the first connection structure close to the overlapping part of the data line is a first edge, the first part of the first connection structure further comprises a second edge away from the overlapping part of the data line, and an edge of the overlapping part of the data line close to the first connection structure is a third edge;
a distance from an orthographic projection of the second edge of the first connection structure of the first sub-pixel on the base substrate to an orthographic projection of the third edge of the overlapping part of the data line of the second sub-pixel on the base substrate is a first distance, a distance from a first edge of the first connection structure of the first sub-pixel to a third edge of an overlapping part of a data line of the first sub-pixel is a second distance, and a ratio of the first distance to the second distance is greater than 14 (see Applicant’s disclosure [0143-0146]).
Regarding claim 17:
The closest art of record singly or in a combination fails to teach or suggest the limitations “the plurality of sub-pixels further comprise a third sub-pixel, and the third sub-pixel (P3, see Fig. 5) is adjacent to the second sub-pixel in the first direction; and a part of the second reset signal line in each of the sub-pixels in the plurality of sub-pixels comprises a transverse part and a first vertical part, the transverse part extends along the second direction and has a first end and a second end that are opposite each other in the second direction, the first vertical part is connected with the first end of the transverse part and extends along the first direction, and an orthographic projection of the transverse part of the second reset signal line in the second sub-pixel on the base substrate is at least partially overlapped with an orthographic projection of the first reset scan signal line in the third sub-pixel on the base substrate, and the first vertical part of the second reset signal line in the second sub-pixel is spaced apart from the active layer of the first reset transistor of the third sub-pixel in the second direction (see Applicant’s disclosure [0223-0228], Fig. 5).
Pertinent art
3. The pertinent art of record (US 20180371131 A1) discloses display device.
Inquiry
4. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Shaheda Abdin whose telephone number is (571) 270-1673.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao could be reached at (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about PAIR system, see http://pari-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAHEDA A ABDIN/Primary Examiner, Art Unit 2621