CTNF 18/839,442 CTNF 85364 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of Group I (claims 1-9 and 11-12) in the reply filed on 5/19/2026 is acknowledged. The traversal is on the grounds that claim 17 was amended to incorporate by reference claim 1 and therefore Groups I and II have common special technical features. This is not found persuasive because as evidenced by the prior art rejection below, claim 1 does not constitute a special technical feature and thus unity of invention is lacking a posteriori there not being a shared technical feature between Group I and Group II defining a contribution over the prior art. Consequently the restriction requirement between Group I and Group II is maintained. Currently, claims 1-9, 11-12, 17-18, 20, 22-26, 28 are pending, but claims 17-18, 20, 22-26, 28 are withdrawn from consideration as directed to non-elected subject matter, and claims 1-9 and 11-12 are examined as follows. The requirement is still deemed proper and is therefore made FINAL. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: “Pixel circuit, driving method, display substrate and apparatus with separate threshold voltage compensation and data writing” . Claim Objections 07-29-01 AIA Claim 12 is objected to because of the following informalities: Claim 12 references claim 1 and therefore should refer to the different elements already described in claim 1 as “the” and not as “a” for proper antecedent basis as follows starting in line 3: “writing, by a the first reset sub-circuit, a the first initial signal provided by a the first initial signal line to a the first node under control of a the first reset control line, in a the threshold compensation stage, writing, by a the second voltage writing sub-circuit, a the threshold voltage of a the driving sub-circuit to a the third node under control of a the compensation control line, and conducting, by a the writing control circuit, the third node and a the fourth node and writing the threshold voltage to the fourth node under control of a the second scan line; in a the data writing stage, writing, by a the first voltage writing sub-circuit, a the data signal provided by a the data line to the third node under control of a the first scan line, writing, by the writing control circuit, the data signal to the fourth node, and coupling, by a the coupling sub- circuit, the signal written to the fourth node to the first node; and providing, by the driving sub-circuit, a the driving signal to the third node under control of the first node” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3, 8 and 12 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Qing in EP-4207162-A1 (IDS 2/17/25 cite #4). The US equivalent was used as a translation (US 2024/0185780) . Regarding claim 1, Qing disclose a pixel circuit (Qing’s Fig. 7), comprising a driving sub-circuit (Qing’s Fig. 7: see 01), a first voltage writing sub-circuit (Qing’s Fig. 7: see 06), a second voltage writing sub-circuit (Qing’s Fig. 7: see 03), a writing control sub-circuit (Qing’s Fig. 7: see 07), a coupling sub-circuit (Qing’s Fig. 7: see wiring between left electrode of T2 and N1 which includes connection circuitry as shown between T2 and DTFT in Fig. 35), a first reset sub-circuit (Qing’s Fig. 7: see 09), and a storage sub-circuit (Qing’s Fig. 7: see 04); wherein the driving sub-circuit (Qing’s Fig. 7: see 01) is coupled to a first node, a second node and a third node (Qing’s Fig. 7: see N1, N2 and N3 respectively), and is configured to provide a driving signal to the third node under control of the first node (Qing’s Fig. 7 and par. 208-209); the first reset sub-circuit (Qing’s Fig. 7: see 09) is coupled to the first node, a first reset control line and a first initial signal line (Qing’s Fig. 7: see 09: see N1, Reset and Vinit respectively), and is configured to write a first initial signal provided by the first initial signal line (Qing’s Fig. 7: see Vinit) to the first node (Qing’s Fig. 7: see N1) under control of the first reset control line (Qing’s Fig. 7 and par. 215: see Reset); the first voltage writing sub-circuit (Qing’s Fig. 7: see 06) is coupled to the third node (Qing’s Fig. 7 and par. 224: see N3 through C2/C1/T2 when T2 is conducting in stage t3), a first scan line and a data line (Qing’s Fig. 7: see Gate1 and Vdata respectively), and is configured to write a data signal provided by the data line (Qing’s Fig. 7: Vdata) to the third node (Qing’s Fig. 7: N3) under control of the first scan line (Qing’s Fig. 7 and par. 221: Gate1) in a data writing stage (Qing’s Fig. 8 and par. 224: see t3); the second voltage writing sub-circuit (Qing’s Fig. 7: see 03) is coupled to the second node, a compensation control line and a second initial signal line (Qing’s Fig. 7: see N2, EM2 and Vref respectively), and is configured to write a threshold voltage of the driving sub-circuit (Qing’s Fig. 7 and par. 210: Vref) to the third node (Qing’s Fig. 7 and par. 224: when T2 is conducting and C1 is Vdata+Vth-Vref) under control of the compensation control line (Qing’s Figs. 7-8: EM2) in a threshold compensation stage (Qing’s Fig. 8 and par. 224: transistors T2 and T3 are conducting during period t4); the writing control sub-circuit (Qing’s Fig. 7: see 07) is coupled to the third (Qing’s Fig. 7: see N3) , a fourth node(Qing’s Fig. 7: see left electrode of transistor T2) and a second scan line (Qing’s Fig. 7: see Gate2), and is configured to conduct the third node and the fourth node under control of the second scan line in the data writing stage and the threshold compensation stage (Qing’s Figs. 7-8: see Gate2 active during data writing in t3 and compensation stage t4); the coupling sub-circuit (Qing’s Fig. 7: see wiring between left electrode of T2 and N1 which includes connection circuitry as shown between T2 and DTFT in Fig. 35) is coupled to the first node (Qing’s Fig. 7: see N1 shown as a connection to DTFT in Fig. 35) and the fourth node (Qing’s Fig. 7: left electrode of transistor T2 shown as a connection to T2 in Fig. 35), and is configured to couple a signal written to the fourth node to the first node (Qing’s Fig. 7: by virtue of being a wiring line); the storage sub-circuit (Qing’s Fig. 7: see 04) is coupled to the first node (Qing’s Fig. 7: N1) and a first power supply line (Qing’s Fig. 7: see VDD [through T8]); and in one display period (Qing’s Fig. 7), the threshold compensation stage is independent of the data writing stage (Qing’s Fig. 7: see t4 independent from t3 because they are enabled by different signals and do not require one another to operate). Regarding claim 3, Qing discloses further comprising a first control sub-circuit (Qing’s Fig. 7: see T8/T5 in 02) and a second control sub-circuit (Qing’s Fig. 7: see T6 in 02); wherein the first control sub-circuit is coupled to the second node, a first control line and the first power supply line (Qing’s Fig. 7: see T8/T5 coupled to N2, EM1 and VDD respectively), and is configured to conduct the first power supply line and the second node under control of the first control line (Qing’s Figs. 7-8 and par. 224: see T6, T5 and T8 turned on by EM1 active); and the second control sub-circuit is coupled to the third node, a second control line and a fifth node (Qing’s Fig. 7: see T6 coupled to N3, EM1 and N5 respectively), and is configured to transmit the drive signal to the fifth node under control of the second control line (Qing’s Fig. 7 and par. 224: driving signal from DTFT to N5 when T6 is conducting when EM1 is active); and the fifth node is coupled to a first electrode of a light emitting element (Qing’s Fig. 7: N5 to OLED), and a second electrode of the light emitting element is coupled to a second power supply line (Qing’s Fig. 7: cathode of OLED to VSS). Regarding claim 8, Qing discloses further comprising a second reset sub-circuit (Qing’s Fig. 7: see 05), which is coupled to the fifth node, a second reset control line, and a third initial signal line (Qing’s Fig. 7: see 05 to N5, EM2 and Vinit respectively) and is configured to write a third initial signal provided by the third initial signal line to the fifth node under control of the second reset control line (Qing’s Fig. 7 and par. 224: when EM2 is active, 05 conducts Vinit to N5). Regarding claim 12, Qing disclose a method for driving a pixel circuit (Qing’s Figs. 7-8), applied to the pixel circuit according to claim 1 (as explained above), comprising: writing, by a the first reset sub-circuit (Qing’s Fig. 7: see 09), a the first initial signal (Qing’s Fig. 7: see Vinit) provided by a the first initial signal line (Qing’s Fig. 7: see Vinit) to a the first node (Qing’s Fig. 7: see N1) under control of a the first reset control line (Qing’s Fig. 7 and par. 215: see Reset), in a the threshold compensation stage (Qing’s Fig. 8 and par. 224: period t4), writing, by a the second voltage writing sub-circuit (Qing’s Fig. 7: see 03), a the threshold voltage of a the driving sub-circuit (Qing’s Fig. 7 and par. 210: Vref) to a the third node (Qing’s Fig. 7 and par. 224: when T2 is conducting and C1 is Vdata+Vth-Vref) under control of a the compensation control line (Qing’s Figs. 7-8: EM2), and conducting, by a the writing control circuit (Qing’s Fig. 7: see 07), the third node and a the fourth node (Qing’s Figs. 7-8: see Gate2 active during data compensation stage t4) and writing the threshold voltage (Qing’s Fig. 7 and par. 210: Vref) to the fourth node(Qing’s Fig. 7: left electrode of transistor T2 shown as a connection to T2 in Fig. 35) under control of a the second scan line (Qing’s Fig. 7: see Gate2); in a the data writing stage (Qing’s Fig. 8 and par. 224: see t3), writing, by a the first voltage writing sub-circuit (Qing’s Fig. 7: see 06), a the data signal provided by a the data line (Qing’s Fig. 7: Vdata) to the third node (Qing’s Fig. 7: N3) under control of a the first scan line (Qing’s Fig. 7 and par. 221: Gate1), writing, by the writing control circuit (Qing’s Fig. 7: see 07), the data signal to the fourth node (Qing’s Figs. 7-8: see Gate2 active during data writing in t3), and coupling, by a the coupling sub- circuit (Qing’s Fig. 7: see wiring between left electrode of T2 and N1 which includes connection circuitry as shown between T2 and DTFT in Fig. 35), the signal written to the fourth node to the first node (Qing’s Fig. 7: by virtue of being a wiring line); and providing, by the driving sub-circuit (Qing’s Fig. 7: see 01), a the driving signal to the third node under control of the first node (Qing’s Fig. 7 and par. 208-209) . Allowable Subject Matter Claims 2, 4-7, 9 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, Qing fails to disclose ALL limitations of claim 1, in addition to “ wherein in one display period the threshold compensation stage is before the data writing stage, and a time length of the threshold compensation stage is longer than a time length of the data writing stage ”. Regarding claim 4, Qing fails to disclose ALL limitation of claims 1+3, in addition to “ wherein a first control signal provided by the first control line is different from a second control signal provided by the second control line ”. Regarding claim 5, Qing fails to disclose ALL limitation of claims 1+3, in addition to “further comprising a third voltage writing sub-circuit, which is coupled to the third node, a third scan line, and a fourth initial signal line and configured to write a fourth initial signal provided by the fourth initial signal line to the third node under control of the third scan Line before the threshold compensation stage” . Dependent claims 6-7 are indicated as allowable for at least the same reasons. Regarding claim 9, the prior art fails to disclose ALL limitations of claims 1+3+8, in addition to “…wherein the third transistor (DTFT), the fourth transistor (T4), the fifth transistor (T8), the sixth transistor (T6), the seventh transistor (T3), and the eighth transistor (T7) are a first type of transistors (Qing’s Fig. 7 and par. 223: all transistors are PMOS); the first transistor (T1) and the second transistor (T2) are a second type of transistors; and a transistor type of the first type of transistors and a transistor type of the second type of transistors are different ”. Regarding claim 11, the prior art fails to disclose ALL limitations of claim 1 in addition to “wherein the storage sub-circuit comprises a first capacitor; the coupling sub-circuit comprises a second capacitor ; a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the first power supply line; and a first electrode of the second capacitor is coupled to the fourth node, and a second electrode of the second capacitor is coupled to the first node ”. The closest prior art is Qing (Figs. 7-8) and does not disclose the limitations required for claims 2, 4-6, 9 and 11. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cao et al. in US 2024/0169915 and Yuan in US 2023/0178008 directed to separating data writing from threshold compensation . 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LILIANA CERULLO/Primary Examiner, Art Unit 2621 Application/Control Number: 18/839,442 Page 2 Art Unit: 2621 Application/Control Number: 18/839,442 Page 3 Art Unit: 2621 Application/Control Number: 18/839,442 Page 4 Art Unit: 2621 Application/Control Number: 18/839,442 Page 5 Art Unit: 2621 Application/Control Number: 18/839,442 Page 6 Art Unit: 2621 Application/Control Number: 18/839,442 Page 7 Art Unit: 2621 Application/Control Number: 18/839,442 Page 8 Art Unit: 2621 Application/Control Number: 18/839,442 Page 9 Art Unit: 2621 Application/Control Number: 18/839,442 Page 10 Art Unit: 2621
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