Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
35 U.S.C. 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103(a) as being unpatentable over Schaefer (Korhonen - US Pub. No. 2005/0120124) in view of (Takaku - US Pub. No. 2008/0155369).
With respect to claims 1 and 9, the Korhonen reference teaches a circuit information memory that stores circuit information ([0103] - Based on the checksum and the received transmissions, statistical information is updated in block 601, parameters depicting packet losses and the distribution of bit errors are formed and feedback messages are transmitted to the transmitting server through feedback channel 507); a processor that repeatedly executes a calculation process for controlling an apparatus based on the circuit information read from the circuit information memory ([0105] - Processing unit 171 controls the operation of the server 111 based on software 175 stored in the first memory 174, such as the transmission of media contents stored beforehand in the second memory (disc) 176 through network interface 172 to the client device 101); and a diagnosis unit that executes a diagnosis process for diagnosing presence or absence of a bit error in the circuit information stored in the circuit information memory ([0085 -0087] - Diagnosis: The packet losses are primarily due to bit errors).
The Korhonen reference does not teach wherein the processor is configured to output, as the calculation result, recent past data corresponding to a case where no bit error is diagnosed by the diagnosis unit, among the calculation results stored in the data memory, or alternative data prepared in advance to correspond to the past data, in a case where the bit error is diagnosed by the diagnosis unit..
The Takaku reference teaches wherein the processor is configured to output, as the calculation result, recent past data corresponding to a case where no bit error is diagnosed by the diagnosis unit, among the calculation results stored in the data memory, or alternative data prepared in advance to correspond to the past data, in a case where the bit error is diagnosed by the diagnosis unit ([0100] - the history table with an error and the history table without an error can be compared by comparing the "history table recorded in the history memory 1101" and the "history table recorded in the history memory of the memory controller 908") , or alternative data prepared in advance to correspond to the past data, in a case where the bit error is diagnosed by the diagnosis unit ([0045] - When the error detecting circuit 203 or 204 detects an error, updating the history memory 201 stops after a predetermined period of time from the time when the error is detected).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Korhonen and Takaku to incorporate wherein the processor is configured to output, as the calculation result, recent past data corresponding to a case where no bit error is diagnosed by the diagnosis unit, among the calculation results stored in the data memory, or alternative data prepared in advance to correspond to the past data, in a case where the bit error is diagnosed by the diagnosis unit into the claimed invention.
The motivation for wherein the processor is configured to output, as the calculation result, recent past data corresponding to a case where no bit error is diagnosed by the diagnosis unit, among the calculation results stored in the data memory, or alternative data prepared in advance to correspond to the past data, in a case where the bit error is diagnosed by the diagnosis unit is to increase the speed of processing ([0060] - Takaku).
With respect to claims 2, the Korhonen reference teaches wherein the diagnosis unit is a scrubbing module that performs a scrubbing process for correcting the bit error, in a case where the bit error is diagnosed via the diagnosis process ([0085 -0087] - using small packets in the transmission, (selective) re-transmissions of packets (only the most important packets are re-transmitted) or adding of redundancy to unprotected packets (that is, using FEC, Forward Error Correction)).
With respect to claims 3, the Korhonen reference teaches wherein the processor temporarily stores the calculation result in the data memory, and discards the calculation result from the data memory, in a case where the bit error is diagnosed by the diagnosis unit ([0085 -0087] - using small packets in the transmission, (selective) re-transmissions of packets (only the most important packets are re-transmitted) or adding of redundancy to unprotected packets (that is, using FEC, Forward Error Correction)).
With respect to claim 4, all of the limitations of claim 1 have been addressed.
The Korhonen reference does not teach wherein the processor is configured to acquire the past data from the data memory..
The Takaku reference teaches wherein the processor is configured to acquire the past data from the data memory ([0100] - the history table with an error and the history table without an error can be compared by comparing the "history table recorded in the history memory 1101" and the "history table recorded in the history memory of the memory controller 908).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Korhonen and Takaku to incorporate teach wherein the processor is configured to acquire the past data from the data memory into the claimed invention.
The motivation for wherein the processor is configured to acquire the past data from the data memory is to increase the speed of processing ([0060] - Takaku).
With respect to claims 5, the Korhonen reference teaches wherein the diagnosis process is executed in parallel with the calculation process by the processor. (See fig. 7, 171 and 175) and ([0105] - Processing unit 171 controls the operation of the server 111 based on software 175 stored in the first memory 174).
With respect to claims 6, the Korhonen reference teaches wherein a processing time of the processor and a diagnosis result of the diagnosis unit are stored in the data memory in association with each other for each of the calculation results ([0081] - accurate information is obtained on the distribution of bit errors (typically a characteristic of a wireless connection) and on packet losses (characteristic both of fixed and wireless networks) and on packet transmission times and on transmission time jitter).
With respect to claim 7, all of the limitations of claim 1 have been addressed.
The Korhonen reference does not teach wherein in a case where a diagnosis result indicating that the bit error is present is obtained a plurality of times in succession by the diagnosis unit, the processor outputs the alternative data as the calculation result...
The Takaku reference teaches wherein in a case where a diagnosis result indicating that the bit error is present is obtained a plurality of times in succession by the diagnosis unit, the processor outputs the alternative data as the calculation result. ([0045] - When the error detecting circuit 203 or 204 detects an error, updating the history memory 201 stops after a predetermined period of time from the time when the error is detected).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Korhonen and Takaku to incorporate wherein in a case where a diagnosis result indicating that the bit error is present is obtained a plurality of times in succession by the diagnosis unit, the processor outputs the alternative data as the calculation result. into the claimed invention.
The motivation for wherein in a case where a diagnosis result indicating that the bit error is present is obtained a plurality of times in succession by the diagnosis unit, the processor outputs the alternative data as the calculation result is to increase the speed of processing ([0060] - Takaku).
With respect to claim 8, all of the limitations of claim 1 have been addressed.
The Korhonen reference does not teach wherein the alternative data is a simulation result related to the calculation result.
The Takaku reference teaches wherein the alternative data is a simulation result related to the calculation result ([0045] - When the error detecting circuit 203 or 204 detects an error, updating the history memory 201 stops after a predetermined period of time from the time when the error is detected).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Korhonen and Takaku to incorporate wherein the alternative data is a simulation result related to the calculation result the claimed invention.
The motivation for wherein the alternative data is a simulation result related to the calculation result to increase the speed of processing ([0060] - Takaku).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EA
8/7/26
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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