Office Action Predictor
Last updated: April 16, 2026
Application No. 18/839,563

HIGH-PERFORMANCE SCL BIT-FLIP DECODER FOR CONCATENATED POLAR CODES

Non-Final OA §101
Filed
Aug 19, 2024
Examiner
TORRES, JOSEPH D
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
British Telecommunications Public Limited Company
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
90%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
758 granted / 972 resolved
+23.0% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
16 currently pending
Career history
988
Total Applications
across all art units

Statute-Specific Performance

§101
14.6%
-25.4% vs TC avg
§103
37.1%
-2.9% vs TC avg
§102
13.8%
-26.2% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 972 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Group I, claims 1 and 3 in the reply filed on 12/03/2025 is acknowledged. The traversal is on the ground(s) that claim 5 has been made to depend from claim 1. This is not found persuasive because the amended language “for decoding a concatenated polar code encoded by the method of claim 1” is intended use language and does not further limit the claim (see MPEP 2112.02). The requirement is still deemed proper and is therefore made FINAL. Claim 5 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made with traverse in the reply filed on 12/03/2025. For the purposes of advancing prosecution the Examiner suggests that the Applicant modify language in the second line of the preamble ( “decoding a concatenated polar code encoded by the method of claim 1”) and the first limitation following the term “comprising:” in the preamble (“receiving a codeword”), to recite respectively: --decoding a concatenated polar codeword encoded by the method of claim 1-- and --receiving a signal comprising the codeword--. Note: upon making the corrections, the Examiner will rejoin claim 5 as dependent on claim 1. In addition, the suggested language will overcome 101 judicial exception issues. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1 and 3 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract mathematical algorithm for generating a codeword using mathematical error correction transformations without significantly more. The claim(s) recite(s) a list of intermediate mathematical transformations that result in obtaining a codeword. This judicial exception is not integrated into a practical application because the abstract algorithm is not combined with the structural element such that when combined with the structural element raises the level to a practical application. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the claim limitations are directed to the abstract algorithm only. As per claim 3:one or more hardware elements can be a general-purpose computer as taught in the Applicant’s specification. A general-purpose computer for storing a software implementation and executing it, is insufficient to overcome a judicial exception. For the purposes of advancing prosecution, the Examiner suggests replacing the preamble in claim 1 to respectively recite: --A method of encoding and transmitting a codeword-- and adding a new limitation at the very end of the claim reciting --transmitting a signal comprising the codeword x1N--. For the purposes of advancing prosecution, the Examiner suggests replacing language in the first line of the preamble in claim 3 to respectively recite: --An apparatus for encoding and transmitting a concatenated polar codeword, comprising-- and adding a new limitation at the very end of the claim reciting --transmitting a signal comprising the codeword x1N--. Allowable Subject Matter The Examiner would like to point out that upon correcting the claims as suggested, above, the claims will be considered for allowance after a final search, as follows (note: the reasons below are based on the current prior Art search, only): the present invention pertains to an encoder and decoder for a triple concatenated code comprising a Parity Check (PC) Code, a CRC code and a polar code. The prior art of record, and in particular Miyazaki; Shunji (US 20190165818 A1), teaches a hybrid approach where Cyclic Redundancy Check (CRC) bits and Parity Check (PC) bits are both used whereby this “CRC agent parity check” structure allows the system to benefit from the error correction blooms of PC bits and the error detection reliability of CRC bits. The prior art however are not concerned with and do not teach, suggest, or otherwise render obvious “A method of encoding, comprising: 1. evaluating reliabilities of N channels under a design parameter Eb/no; selecting M₀ channels of the N channels based on a relative reliability of each channel; constructing a polar code of M₀ information bits, the M₀ information bits arranged with a front and a rear; constructing a cyclic redundancy checking (CRC) code with KCRC additional bits; attaching the KCRC additional bits to the rear of the Mo information bits; constructing a Parity Check (PC) code with Kpc parity bits by: partitioning the M₀ information bits into Kpc segments, wherein each of the Kpc segments corresponds to a PC equation, wherein constructing the PC equation comprises: generating channel reliability data; selecting non-frozen bits according to the channel reliability data; dividing the selected non-frozen bits into K segments; evaluating, sequentially, each bit of each segment to select a most unreliable bit from each segment that has not already been selected; and storing selected bits as a parity set, wherein the PC equation for each segment of the Kpc segments is associated with a sum of a parity check bit of the segment and only the most unreliable bit of each preceding segment that has not already been selected; inserting the Kpc parity bits at proper locations to yield a bit string, wherein the bit string is a concatenation of the M₀ information bits, the attached KCRC additional bits, and the inserted Kpc parity bits; inserting frozen bits to the bit string and setting the frozen bits to 0; feeding the bit string into a polar encoder; and obtaining a codeword x₁N” as taught by claim 1. Hence the prior art taken alone or in any combination fail to teach the claimed novel feature in claim 1. The prior art however are not concerned with and do not teach, suggest, or otherwise render obvious “An apparatus for encoding concatenated polar code, comprising: 3. one or more hardware elements configured to: evaluate reliabilities of N channels under a design parameter Eb/no and select Mo channels of the N channels based on a relative reliability of each channel; construct a polar code of M₀ information bits, the M₀ information bits arranged with a front and a rear; construct a cyclic redundancy checking (CRC) code with KCRC additional bits and attach the KCRC additional bits to the rear of the Mo information bits; construct a Parity Check (PC) code with KPC parity bits by: partitioning the M₀ information bits into Kpc segments, wherein each of the Kpc segments corresponds to a PC equation, wherein constructing the PC equation comprises: generating channel reliability data, selecting non-frozen bits according to the channel reliability data, dividing the selected non-frozen bits into K segments, evaluating, sequentially, each bit of each segment to select a most unreliable bit from each segment that has not already been selected, and storing selected bits as a parity set, wherein the PC equation for each segment of the Kpc segments is associated with a sum of a parity check bit of the segment and only the most unreliable bit of each preceding segment that has not already been selected; insert the parity bits at proper locations to yield a bit string, wherein the bit string is a concatenation of the M information bits, the attached KCRC additional bits, and the inserted parity bits; insert frozen bits to the bit string and setting the frozen bits to 0; and feed the bit string into a polar encoder and obtain a codeword X1ⁿ” as taught by claim 3. Hence the prior art taken alone or in any combination fail to teach the claimed novel feature in claim 3. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure US 20230155606 A1 is directed to determining the reliability of sub channels to better select which bits should be “frozen” in which you carry information it introduces a refined method for calculating sub channel reliability based on specific code rates improved performance in 5G systems; and is a good teaching reference. US 20200186170 A1 is directed to a method for inserting parity check bits into a polar code sequence using specific PC functions to create dependencies between bits, which helps the decoder “prune” incorrect paths early during a successive cancellation list (SCL) search; and, is a good teaching reference. US 20190372591 A1 is directed to a rate matching process whereby specific interleaving of puncturing patterns that ensure the most reliable bits of protected during transmission are used; and, is a good teaching reference US 20190165818 A1 is directed to a hybrid approach where Cyclic Redundancy Check (CRC) bits and Parity Check (PC) bits are both used whereby this “CRC agent parity check” structure allows the system to benefit from the error correction blooms of PC bits and the error detection reliability of CRC bits1 F. Cheng, A. Liu, J. Ren and K. Feng, "CRC-Aided Parity-Check Polar Coding," in IEEE Access, vol. 7, pp. 155574-155583, 2019. This paper is directed to a “concatenated” coding scheme where CRC bits are distributed within the information sequence rather than just at the end. Because CRC bits are placed in the middle, the decoder can stop immediately if an error is detected, saving power reducing latency. This paper is a good teaching reference. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH D TORRES/ Primary Examiner, Art Unit 2112
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Prosecution Timeline

Aug 19, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection — §101
Mar 24, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
90%
With Interview (+11.6%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 972 resolved cases by this examiner. Grant probability derived from career allow rate.

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