DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 19 are objected to because of the following informalities:
As to claim 1, “the first driving unit” recited in line 6 should be changed to “ the first gate driving unit” in order to be consistent with “a first gate driving unit” previously recited in the claim.
As to claim 1, “the second driving unit” recited in line 6 should be changed to “ the second gate driving unit” in order to be consistent with “a second gate driving unit” previously recited in the claim. Appropriate correction is required.
As to claim 1, “a buffer unit” recited in line 6 of the claim should be changed to “the buffer unit” since “a buffer unit” was previously recited in the claim. Appropriate correction is required.
As to claim 19, “the low voltage signal of the second gate signal” recited in line 7 of the claim should be changed to “ a low voltage signal of the second gate signal”, since “a low voltage signal of the second gate signal” was not previously recited in the claim. Appropriate correction is required.
As to claim 19, “the low voltage signal of the third gate signal” recited in line 8 of the claim should be changed to “a low voltage signal of the third gate signal”, since “a low voltage signal of the third gate signal” was not previously recited in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 14-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by In (US 2021/0383760 A1).
As to claim 1, In teaches a display substrate ([0086]: substrate), comprising:
a gate signal line, comprising a first gate signal line and a second gate signal line spaced apart from each other (see first gate power line VGHL1, second gate power line VGHL2 in Fig. 5) wherein each of the first gate signal line and the second gate signal line is applied with a first voltage ([0080]: gate power lines VGHL have a same voltage level);
a first gate driving unit (stage GC_ST1 in Fig. 5) a second gate driving unit (stage GC_ST2 in Fig. 5) comprising a buffer unit ([0149];[0151]: transistors T9, T10, Fig. 5), wherein each of the first driving unit (stage GC_ST1 in Fig. 5) and the second driving unit (stage GC_ST2 in Fig. 5) comprises a buffer unit (transistors T9, T10 in Fig. 5; [0149];[0151]), the buffer unit comprises a first transistor (T9 in Fig. 5), a second transistor (T10 in Fig. 5), and an output electrode configured to output a gate control signal ([0079];[0152-0153]: output terminal OUT, Fig. 5), a first electrode of the first transistor (T9 in Fig. 5) and a first electrode of the second transistor (T10 in Fig. 5) are connected to the output electrode ([0152-0153]: output terminal OUT, see Fig. 5), and a second electrode of the first transistor (T9 in Fig. 5) is connected to the gate signal line (first gate power line VGHL1, second gate power line VGHL2 in Fig. 5); and
pixel circuits electrically connected to the output electrode of the buffer unit ([0079];[0152]: output terminal OUT, Fig. 5; Abstract: pixels), wherein the pixel circuits comprise a pixel group in odd-numbered rows (pixels connected to the gate lines GCL1, GCL2 in Fig. 5; Abstract;[0079]) and a pixel group in even-numbered rows (pixels connected to the gate lines GCL3, GCL4 in Fig. 5; Abstract;[0079]), and the pixel group comprises at least two rows of pixel circuits (pixels connected to the gate lines GCL1, GCL2 in Fig. 5, pixels connected to the gate lines GCL3, GCL4 in Fig. 5; Abstract; [0079]),
wherein the first gate signal line (VGHL1 line in Fig. 5) is connected to the second electrode of the first transistor (T9 in Fig. 5) of the first gate driving unit (stage GC_ST1 in Fig. 5) so that the first gate driving unit (stage GC_ST1 in Fig. 5) provides the gate control signal to the pixel group in odd-numbered rows (pixels connected to the gate lines GCL1, GCL2 in Fig. 5; Abstract;[0079]), and the second gate signal line (VGHL2 line in Fig. 5) is connected to the second electrode of the first transistor (T9 in Fig. 5) of the second gate driving unit (stage GC_ST2 in Fig. 5) so that the second gate driving unit (stage GC_ST2 in Fig. 5) provides the gate control signal to the pixel group in even-numbered rows (pixels connected to the gate lines GCL3, GCL4 in Fig. 5; Abstract;[0079]).
As to claim 2, In teaches the display substrate according to claim 1, further comprising: a reference gate signal line applied with a second voltage (VGL line in Fig. 5; [0191]: reference gate power voltage VGL), wherein the reference gate signal line (VGL line in Fig. 5; [0191]: reference gate power voltage VGL) is connected to a second electrode of the second transistor (T10 in Fig. 5) of the buffer unit ([0149];[0151]).
As to claim 3, In teaches the display substrate according to claim 2, wherein each of the first gate driving unit (stage GC_ST1 in Fig. 5) and the second gate driving unit (stage GC_ST2 in Fig. 5) further comprises a scan unit (T8 in Fig. 5) connected to the gate signal line (first gate power line VGHL1, second gate power line VGHL2 in Fig. 5).
As to claim 4, In teaches the display substrate according to claim 3, wherein the scan unit (T8 in Fig. 5) in the first gate driving unit (stage GC_ST1 in Fig. 5) is electrically connected to the first gate signal line (first gate power line VGHL1 in Fig. 5), and the scan unit (T8 in Fig. 5) in the second gate driving unit (stage GC_ST2 in Fig. 5) is electrically connected to the second gate signal line (second gate power line VGHL2 in Fig. 5).
As to claim 5, In teaches the display substrate according to claim 3, wherein the scan unit (T8 in Fig. 5) in the first gate driving unit (stage GC_ST1 in Fig. 5) is electrically connected to the second gate signal line (VGHL2 line in Fig. 5), and the scan unit (T8 in Fig. 5) in the second gate driving unit (stage GC_ST2 in Fig. 5) is electrically connected to the first gate signal line ([0091]: first gate power line VGHL1; note that the claim does not recite “directly” connected. All of the elements in Fig. 5 are connected to each other).
As to claim 7, In teaches the display substrate according to any one of claim 4, wherein, the reference gate signal line (VGL line in Fig. 5; [0191]: reference gate power voltage VGL) is connected to the scan unit (T8 in Fig. 5) in the first gate driving unit (stage GC_ST1 in Fig. 5); and the reference gate signal line (VGL line in Fig. 5; [0191]: reference gate power voltage VGL) is connected to the scan unit (T8 in Fig. 5) in the second gate driving unit (stage GC_ST2 in Fig. 5).
As to claim 14, In teaches the display substrate according to claim 1, wherein the display substrate ([0093-0094]: substrate) comprises at least two first gate signal lines (vertical first gate power line VGHL1, and horizontal line directly connected to vertical first gate power line VGHL1 in Fig. 4) and at least two second gate signal lines (vertical second gate power line VGHL2, and horizontal line directly connected to vertical second gate power line VGHL2 in Fig. 4).
As to claim 15, In teaches the display substrate according to claim 1, wherein, each pixel group in the pixel circuits comprises a first row of pixel circuits and a second row of pixel circuits arranged in parallel with the first row of pixel circuits (pixels connected to the gate lines GCL1, GCL2 in Fig. 5; Abstract: pixels);
the first row of pixel circuits and the second row of pixel circuits comprise a common N-type gate electrode (Abstract: pixels connected to the gate lines; [0109-0110]; gate electrode of N-type transistor M3 in Fig. 3); and
the first row of pixel circuits comprises a first P-type gate electrode (Abstract: pixels connected to the gate lines; [0109-0110]; gate electrode of P-type transistor M2 in Fig. 3), and the second row of pixel circuits comprises a second P-type gate electrode (Abstract: pixels connected to the gate lines; [0109-0110]; gate electrode of P-type transistor M7 in Fig. 3).
As to claim 16, In teaches the display substrate according to claim 15, wherein the output electrode comprises: a first output electrode connected to the N-type gate electrode so as to provide a first gate signal to the N-type gate electrode (gate electrode of N-type transistor M3 in Fig. 3;[0115-0116]: gate electrode of t transistor M3 connected to gate line GCLn);
a second output electrode connected to the first P-type gate electrode so as to provide a second gate signal to the first P-type gate electrode (gate electrode of P-type transistor M2 in Fig. 3;[0113-0114]: gate electrode of transistor M2 connected to gate line GWLn); and
a third output electrode connected to the second P-type gate electrode so as to provide a third gate signal to the second P-type gate electrode (gate electrode of P-type transistor M7 in Fig. 3;[0122-0123]: gate electrode of transistor M7 connected to gate line GBLn).
As to claim 17, In teaches the display substrate according to claim 16, wherein a low voltage signal in the second gate signal ([0114]: write gate signal is supplied to the write gate line GWLn; Fig. 7B shows write gate signal GW[1]) does not overlap with a low voltage signal in the third gate signal in terms of timing sequence ([0123]: bypass gate signal is supplied to the bypass gate line GBLn, Fig. 7B shows write gate signal GW[1] does not overlap bypass gate signal GB[1] and GB[2]).
As to claim 18, In teaches the display substrate according to claim 3, further comprising: a first clock signal line (CLKL1 in Fig. 4), a second clock signal line (CLKL2 in Fig. 4), an initial signal line (RSTL line in Fig. 4), and a control signal line (STPL line in Fig. 4) connected to the scan unit(T8 in Figs. 4-5;[0148]: input terminal IN0 connected to the start signal line STPL; note that the claim does not recite “directly” connected. All of the elements in Figs. 4-5 are connected to each other).
As to claim 20, In teaches a display device ([0002]: display device), comprising the display substrate of claim 1 (see rejection for claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over In (US 2021/0383760 A1).
As to claim 6, In teaches the display substrate according to claim 3, but the particular embodiment does not disclose wherein, the gate signal line further comprises a third gate signal line applied with the first voltage, and the third gate signal line is spaced apart from the first gate signal line and the second gate signal line; the third gate signal line is connected to the scan unit in the first gate driving unit; and the third gate signal line is connected to the scan unit in the second gate driving unit.
However, in another embodiment, In teaches wherein, the gate signal line further comprises a third gate signal line ([0259]: third gate power line VGHL3) applied with the first voltage ([0034]: same voltage;[0260]), and the third gate signal line (third gate power line VGHL3, Fig. 14) is spaced apart from the first gate signal line ([0260]: first gate power line VGHL1, Fig. 14) and the second gate signal line([0260]: second gate power line VGHL2, Fig. 14); the third gate signal line (VGHL3 in Fig. 14) is connected to the scan unit (T8 in Fig. 14) in the first gate driving unit (stage GC_ST1 in Fig. 14); and the third gate signal line ([0259]: third gate power line VGHL3) is connected to the scan unit (T8 in Fig. 14) in the second gate driving unit (stage GC_ST2 in Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display substrate of In such that the gate signal line further comprises the third gate signal line applied with the first voltage, wherein the third gate signal line is spaced apart from the first gate signal line and the second gate signal line, and the third gate signal line is connected to the scan unit in the first gate driving unit and the second gate driving unit as taught by another embodiment, in order to reduce or prevent a luminance difference due to a fluctuation of a gate signal.
Allowable Subject Matter
Claims 8-13 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten to overcome the claim objection(s) as set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
