DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) filed on August 20th, 2024, March 18th, 2025, and July 9th, 2025, are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is a possible suggestion: Semiconductor Device with Connecting Electrodes Between a Plurality of Substrates Without Extension Past Unconnected Substrate Surfaces.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the resin" in line 5. There is insufficient antecedent basis for this limitation in the claim. “The resin” is only introduced in claim 2, upon which claim 12 does not currently depend. For examination purposes, claim 12 is interpreted as follows:
Claim 12: The semiconductor device according to claim 1, wherein at least one of the first connecting electrode and the second connecting electrode provided to extend outward from the fourth side surface in plan view has a bend
and the bend bends an end extending outward from the fourth side surface in plan view to a side of the upper surface of the substrate.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8, and 13 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hatano et al., US PGPub 2018/0145007 A1 (hereinafter referred to as “Hatano”).
Regarding claim 1, Hatano discloses a semiconductor device comprising (FIGs. 61, 64, power module 1, [0131]):
a substrate (FIGs. 61, 64, ceramics substrate 21, [0574]);
at least one semiconductor element provided over an upper surface of the substrate (FIGs. 61, 64, SiC MOSFETs Q1, Q4, [0568]);
a P electrode electrically connected to the semiconductor element and provided to extend outward from a first side surface of the substrate in plan view (FIGs. 61, 62A, positive-side power terminal P extending outward from a first side of ceramics substrate 21, electrically connected to electrode pattern 25D1 and thus to SiC MOSFETs Q1, Q4, [0574, 0582-0583]);
an AC electrode electrically connected to the semiconductor element and provided to extend outward from a second side surface opposite the first side surface in plan view (FIGs. 61, 62A, output terminal electrodes O extending outward from a third side opposite the first side of ceramics substrate 21, electrically connected to electrode pattern 25D4 which functions as a source electrode for SiC MOSFETs Q1, Q4 and thus, output terminal electrodes are electrically connected to Q1, [0574, 0582, 0584]);
a first connecting electrode electrically connected to the semiconductor element and the AC electrode and provided to extend outward from at least one of a third side surface intersecting with the first side surface and a fourth side surface opposite the third side surface in plan view (FIGs. 61, 62A-62B, gate terminals GT1, GT4 electrically connected to SiC MOSFETs Q1, Q4 and output terminal electrodes O through GL1/GW1, GL4/GW4, extending outward from a second side adjacent to the first side of the ceramics substrate 21 and a fourth side opposite the second, [0574, 0576-0577, 0588]);
and a second connecting electrode electrically connected to the semiconductor element and provided to extend outward from at least one of the third side surface and the fourth side surface in plan view (FIGs. 61, 62A-62B, source sense terminals SST1, SST4 electrically connected to SiC MOSFETs Q1, Q4 and output terminal electrodes O through SL1/SSW1, SL4/SSW4, extending outward from a second side adjacent to the first side of the ceramics substrate 21 and a fourth side opposite the second, [0574, 0576-0577, 0588]),
wherein the first connecting electrode does not overlap any of the P electrode and the AC electrode in plan view above the substrate, and the second connecting electrode does not overlap any of the P electrode and the AC electrode in plan view above the substrate (FIGs. 61, 62A, as seen in plan view (i.e., FIG. 62A), none of GT1/GT4, SST1/SST4 overlap with the positive-side power terminal P or output terminal electrodes O).
Regarding claim 2, Hatano discloses the semiconductor device according to claim 1, as discussed above.
Hatano further discloses further comprising a resin provided over the upper surface of the substrate to cover the semiconductor element, a portion of the P electrode, a portion of the AC electrode, a portion of the first connecting electrode, and a portion of the second connecting electrode (FIGs. 61, 64, resin molding layer 115 covering a portion of positive-side power terminal P, output terminal electrodes O, gate terminals GT1, GT4, and source sense terminals SST1, SST4[0571, 0574]),
wherein the first connecting electrode does not overlap any of the P electrode and the AC electrode in plan view in the resin, and the second connecting electrode does not overlap any of the P electrode and the AC electrode in plan view in the resin (FIGs. 61, 62A, 64, as seen in plan view (i.e., FIG. 62A), none of GT1/GT4, SST1/SST4 overlap with the positive-side power terminal P or output terminal electrodes O in plan view in the resin).
Regarding claim 3, Hatano discloses the semiconductor device according to claim 2, as discussed above.
Hatano further discloses further comprising an N electrode electrically connected to the semiconductor element and provided to extend outward from the first side surface in plan view, wherein the second connecting electrode is electrically connected to the N electrode (FIGs. 61, 62A, 64, negative-side power terminal N extending outward from the first side of the ceramics substrate 21, electrically connected to SST1/SST4 and SiC MOSFETs Q1, Q4 through electrode pattern 25DN and leadframe SM4, [0574, 0582, 0585-0586]).
Regarding claim 4, Hatano discloses the semiconductor device according to claim 3, as discussed above.
Hatano further discloses wherein the resin is provided to cover a portion of the N electrode, the first connecting electrode does not overlap the N electrode in plan view in the resin, and the second connecting electrode does not overlap the N electrode in plan view in the resin (FIGs. 61, 62A, 64, resin molding layer 115 covering a portion of negative-side power terminal N, none of GT1/GT4, SST1/SST4 overlap with the negative-side power terminal N in plan view in the resin).
Regarding claim 8, Hatano discloses the semiconductor device according to claim 3, as discussed above.
Hatano further discloses wherein the N electrode provided to extend from the first side surface is adjacent to the P electrode provided to extend from the first side surface in plan view (FIGs. 61, 62A, negative-side power terminal N at a first side of the ceramics substrate 21 adjacent to positive-side power terminal P and extends from the first side, [0574]).
Regarding claim 13, Hatano discloses the semiconductor device according to claim 1, as discussed above.
Hatano further discloses wherein a semiconductor of the semiconductor element comprises SiC (FIGs. 61, 62A, SiC MOSFETs Q1, Q4, [0568]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hatano as applied to claim 3 above, and further in view of Gotou, US PGPub 2011/0127061 A1.
Regarding claim 5, Hatano discloses the semiconductor device according to claim 3, as discussed above.
Hanato does not explicitly disclose that the negative-side power terminal N be over an upper surface of the resin molding layer, i.e., wherein the N electrode is disposed over an upper surface of the resin.
However, Gotou, which is directed to bus bar assemblies for semiconductor power modules, does teach an electrode (i.e., a bus bar assembly) disposed on an upper surface of a resin is beneficial for minimizing size of a semiconductor device and misalignment between bus bars and (Gotou FIGs. 1, 2, second bus bar 22 on resinous body 3, [0013, 0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Hatano with the electrode placement teachings of Gotou for the benefit of minimizing size of the semiconductor device and misalignment between the power terminals and resin to improve reliability of the device.
Regarding claim 6, Hatano discloses the semiconductor device according to claim 5, as discussed above.
Hatano in view of Gotou (Hatano/Gotou) further discloses wherein the resin has at least one protrusion on the upper surface thereof, and the N electrode has at least one hole into which the protrusion is fitted at a position where the N electrode overlaps the protrusion in plan view (Gotou FIGs, 1, 2, bosses 33 on seating surface 34 of resinous body 3, second bus bar 22 with positioning holes 223 and front openings 32, [0044, 0048-0049]).
Regarding claim 7, Hatano discloses the semiconductor device according to claim 5, as discussed above.
Hatano/Gotou further discloses wherein the resin has at least one guide on the upper surface thereof, and the N electrode over the upper surface of the resin is disposed adjacent to the guide in plan view (Gotou, FIGs. 1, 2, bosses 33 on seating surface 34 of resinous body 3, second bus bar 22 over seating surface 34, with plate body 221 of second bus bar 22 adjacent to bosses 33, [0048-0049]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hatano as applied to claim 3 above, and further in view of Masunaga et al., US Patent No. 9379040 B2 (hereinafter referred to as “Masunaga”).
Regarding claim 9, Hatano discloses the semiconductor device according to claim 3, as discussed above.
Hatano further discloses wherein the N electrode provided to extend from the first side surface the P electrode provided to extend from the first side surface in plan view (Hatano FIG. 61, negative-side power terminal N at a first side of the ceramics substrate 21 and extends outward from the first side, [0574]).
However, Hatano does not explicitly teach that the negative-side power terminal N overlaps with the positive-side power terminal P in plan view.
Masunaga, which is directed to a similar semiconductor device for power conversion with assorted electrodes around a substrate to minimize size, does teach to have the power terminals overlap in plan view (Masunaga FIGs. 10 (perspective view), 11 (cross-sectional view), first and second power terminal 461a, 461b clearly overlap in plan view (i.e., in top down view, or in other words, if the perspective view of FIG. 10 were rotated to the left 90°). One of ordinary skill in the art would recognize that such overlap of the power terminals would be beneficial to reduce size of the semiconductor device in a direction (e.g., by overlapping the power terminals in a vertical direction, the size of the device in a horizontal direction can be reduced or minimized).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Hatano with the overlapping power terminal teachings of Masunaga for the benefit of reducing size of a semiconductor device
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hatano as applied to claim 1 above, and further in view of Minato et al., US PGPub 2010/0327709 A1 (hereinafter referred to as “Minato”).
Regarding claim 10, Hatano discloses the semiconductor device according to claim 1, as discussed above.
Hatano further discloses wherein the substrate comprises a plurality of substrates (Hatano FIG. 69, a plurality of power modules 11, 12, 13, [0622]),
the semiconductor element, the P electrode, the AC electrode, the first connecting electrode, and the second connecting electrode are provided to each of the substrates (Hatano FIGs. 62A, 69, power modules 11, 12, 13, are the same as power module 1 with each having a positive-side power terminal P at a first side of the ceramics substrate 21, output terminal ) at a third side opposite the first, gate terminal GT1 and source sense terminal SST1 at second side adjacent the first, gate terminal GT4 and source sense terminal SST4 at a fourth side opposite the second, [0574]),
the plurality of substrates include a first substrate and a second substrate arranged adjacent to each other (Hatano FIG. 69, power modules 11, 12, 13 are adjacent to each other),
the first substrate and the second substrate are arranged so that the fourth side surface of the first substrate and the third side surface of the second substrate oppose each other (Hatano FIG. 69, power modules 11 and 12 arranged so second side with GT1, SST1 extending outward is opposite fourth side with GT5, SST5 extending outward),
the first connecting electrode provided to extend outward from the fourth side surface of the first substrate in plan view and the first connecting electrode provided to extend outward from the third side surface of the second substrate in plan view (Hatano FIG. 69, GT1 (i.e., a “first connecting electrode”) of power module 11 extending outward from the second side and GT5 (i.e., a “first connecting electrode”) of power module 11 extending outward from the fourth side),
and the second connecting electrode provided to extend outward from the fourth side surface of the first substrate in plan view and the second connecting electrode provided to extend outward from the third side surface of the second substrate in plan view (Hatano FIG. 69, SST1 (i.e., a “second connecting electrode”) of power module 11 extending outward from the second side and SST5 (i.e., a “second connecting electrode”) of power module 11 extending outward from the fourth side).
Hatano does not explicitly disclose that the first connecting electrode of the first substrate extending outward from the fourth side surface and the first connecting electrode of the second substrate extending outward from the third side surface are connected.
However, Minato, which is directed to a semiconductor module for power distribution purposes in a coil terminal, teaches a plurality of substrates with each having P, AC, and connecting electrodes and the respective connecting electrodes of each of the substrates connected together (Minato FIGs. 1, 4, 8, control terminals 509 on a first side (top side wall surface 111), coil terminal 508 on a second side opposite the first (bottom side wall surface 111), and first and second bus bars 16, 17 on third side intersecting with the first and a fourth side opposite the third [0083, 0085, 0090]) and using the bus bars to connect multiple semiconductor modules (i.e., bus bars 16, 17 connecting from a fourth side of semiconductor module 501 with the corresponding bus bars 16, 17 extending from a third side of semiconductor module 502) for the benefit and purpose of acting as an inverting circuit as part of a power circuit for controlling an external motor in a space-saving way to reduce the overall size of the motor (Minato [0110]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure of Hatano with the connection teachings of Minato such that
the first connecting electrode provided to extend outward from the fourth side surface of the first substrate in plan view and the first connecting electrode provided to extend outward from the third side surface of the second substrate in plan view are connected (Minato FIGs. 1, 4, 8, first bus bar 16 on fourth side opposite the third of semiconducting module 501 connected with first bus bar 16 on a third side of semiconducting module 502 [0083, 0085, 0090]),
and the second connecting electrode provided to extend outward from the fourth side surface of the first substrate in plan view and the second connecting electrode provided to extend outward from the third side surface of the second substrate in plan view are connected (Minato FIGs. 1, 4, 8, second bus bar 17 on fourth side opposite the third of semiconducting module 501 connected with second bus bar 17 on a third side of semiconducting module 502 [0083, 0085, 0090]).
for the benefit of reducing overall device size, particularly when connecting two or more devices for inverter circuit purposes.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hatano as applied to claim 1 above, and further in view of Soyano, US PGPub 2016/0035646 A1.
Regarding claim 12, Hatano discloses the semiconductor device according to claim 1, as discussed above.
Hatano further discloses wherein at least one of the first connecting electrode and the second connecting electrode provided to extend outward from the fourth side surface in plan view has a bend outside the resin (FIG. 61, first connecting electrode GT1/GT4, second connecting electrode SST1/SST4 extend outward from fourth side with a bend).
While Hatano does bend the connecting electrodes toward a side of the upper surface of the substrate, Hatano does not explicitly teach
and the bend bends an end extending outward from the fourth side surface in plan view to a side of the upper surface of the substrate.
However, Soyano, which is directed to a similar semiconductor device with a power semiconductor sealed in resin with outwardly extending leads, does teach to bend an end of the connecting electrodes extending outward from a side surface of the substrate to a side of the upper surface of the substrate (Soyano FIGs. 31-32, external lead pins 81a extend outward and bend in the Z direction to a side of the upper side of the surface, bending of the connecting electrodes/external lead pins [0156, 0159]). One of ordinary skill in the art would recognize that such a configuration of the external lead pins would be beneficial in solving a main problem of minimizing size of the semiconductor device by reducing the size of the device in at least one direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Hatano with the connecting electrode bending teachings of Soyano such that
and the bend bends an end extending outward from the fourth side surface in plan view to a side of the upper surface of the substrate (Soyano FIGs. 31-32, external lead pins 81a extend outward and bend in the Z direction to a side of the upper side of the surface, bending of the connecting electrodes/external lead pins [0156, 0159])
for the benefit of miniaturizing the device by reducing size in at least one direction through bending of the connecting electrodes.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, none of the prior art taken alone or in combination teaches the semiconductor device according to claim 10, wherein at least one of the first connecting electrode and the second connecting electrode is not provided to extend from at least one of the third side surface of the first substrate and the fourth side surface of the second substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ikeda et al., US PGPub 2011/0037166 A1, which is directed to a similar device with a power semiconductor and lead frame for distribution thereof, connecting two substrates with power/output terminal electrodes.
Umeda et al., US PGPub 2023/0009548 A1, which is directed to a semiconductor device with protrusions and alignment pins embedded in resin for guidance and alignment of bus bar electrodes.
Fukumoto et al., US PGPub 2023/0395470 A1, which is directed to a power module using power semiconductors and with a molding and electrode design similar to the instant invention, and an additional bent lead frame structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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