DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5-6, 8, 10, 15, 22 and 24 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ille et al (US Publication No. 20210376601).
Regarding claim 1, Ille discloses an electrostatic discharge (ESD) protection device (i.e., such as ESD 440; see for example fig. 4D as shown below, para. [0051]- [0052]) coupled between a first node (VDD) and a second node (VSS), the ESD protection device (440) comprising: a first branch (AA) between the first node (VDD) and the second node (VSS), the first branch (AA) comprising a switching device (402) and a triggering device (444) coupled to the switching device (402), the triggering device (444) configured to (i.e., such as configured; see for example fig. 4D as shown below, para. [0051]- [0052]) switch on (i.e., such as SCR is ON; see for example fig. 4D as shown below, para. [0051]- [0052]) the switching device (402) during an ESD event (i.e., such as any ESD event; see for example fig. 4D as shown below, para. [0051]- [0052]); a second branch (BB) between the first node (VDD) and the second node (VSS), the second branch (BB) comprising a stack of transistors (M1, M2), wherein an interconnection node (X) interconnects (i.e., such as X connects the drain of M1 to the source of M2; see for example fig. 4D as shown below, para. [0051]- [0052]) a first transistor (M1) and a second transistor (M2) of the stack (M1, M2), wherein the second branch (BB) is electrically connected (i.e., such as electrically connected; see for example fig. 4D as shown below, para. [0051]- [0052]) such that, in operation (i.e., such as during operation; see for example fig. 4D as shown below, para. [0051]- [0052]), a direct current (DC) voltage drop (V2) between the interconnection node (X) and the first node (VDD) is lower than (i.e., such as V2 < V1; see for example fig. 4D as shown below, para. [0051]- [0052]) a DC voltage applied (V1) between the second node (VSS) and the first node (VDD).
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Regarding claim 3, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the second branch (BB) is connected to the first branch (AA) via a branch connection node (Y) which is different from (i.e., such as Y is different from VDD and VSS; see for example fig. 4D as shown above, para. [0051]- [0052]) the first (VDD) and the second node (VSS).
Regarding claim 5, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the branch connection node (Y) is electrically connected (i.e., such as Y is electrically connected to Z; see for example fig. 4D as above below, para. [0051]- [0052]) to a triggering node (Z) of the triggering device (444) of the first branch (AA).
Regarding claim 6, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the first branch (AA) comprises a holding device (422) connected in series (i.e., such as 422 is in series with SCR 402; see for example fig. 4D as above below, para. [0051]- [0052]) with the switching device (402) between the first (VDD) and the second node (VSS), wherein the holding device (422) comprises at least one diode (i.e., such as diode 422; see for example fig. 4D as above below, para. [0051]- [0052]).
Regarding claim 8, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the stack of transistors (M1, M2) is a stack (M1, M2) of at least two (M1 and M2) metal oxide semiconductor (MOS) transistors (i.e., such as M1 and M2 are MOS version; see for example fig. 4D as above below, para. [0051]- [0052]).
Regarding claim 10, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the switching device (402) comprises a silicon-controlled-rectifier (SCR) (SCR 402), wherein the triggering device (444) is connected (i.e., such as 444 is connected to terminal T of SCR 402; see for example fig. 4D as above below, para. [0051]- [0052]) between a trigger tap (T) of the SCR (SCR 402) and one (i.e., such as one T is connected to VSS via element 408 and one T is connected to VDD via element 432; see for example fig. 4D as above below, para. [0051]- [0052]) of the second node (VSS) and the first node (VDD).
Regarding claim 15, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the triggering device (444) comprises at least one diode (i.e., such as 444 is set of diodes; see for example fig. 4D as above below, para. [0051]- [0052]).
Regarding claim 22, Ille discloses the ESD protection device (i.e., such as ESD 440; see for example fig. 4D as shown above, para. [0051]- [0052]); wherein the second branch (BB) is connected (i.e., such as BB is connected via X and Y to AA; see for example fig. 4D as above below, para. [0051]- [0052]) to the first branch (AA) via a branch connection node (Y) that is different (i.e., such as Y is different from VDD and VSS; see for example fig. 4D as above below, para. [0051]- [0052]) than the first node (VDD) and the second node (VSS). And, for the rest of the limitations/features in claim 22 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Regarding claim 24, is rejected for the same reasons that have already been stated/discussed above in rejected claim 5. {See rejection of claim 5}
Allowable Subject Matter
Claims 2, 4, 9, 12-14 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Ille teaches the invention set forth above. However, Ille does not particularly teach wherein the stack of the transistors is a stack of n transistors, and wherein the stack is electrically connected such that, in operation, at most (100/n + 20) % of the DC voltage is applied between the second and the first node.
Hence claim 2 will be deemed allowable if rewritten in an independent form.
Regarding claim 4, Ille teaches the invention set forth above. However, Ille does not particularly teach wherein the branch node connects the interconnection node to a gate of a transistor in the stack of transistors of the second branch.
Hence claim 4 will be deemed allowable if rewritten in an independent form.
Regarding claim 9, Ille teaches the invention set forth above. However, Ille does not particularly teach wherein each of the transistors of the stack has a voltage rating below 2.0V.
Hence claim 9 will be deemed allowable if rewritten in an independent form.
Regarding claim 12, Ille teaches the invention set forth above. However, Ille does not particularly teach further comprising a transient detector, coupled between the first node and the second node or between the first node and the interconnection node, the transient detector comprising a resistive element and a capacitive element, wherein a gate or a base of at least one transistor of the stack is connected to an intermediate node between the resistive element and the capacitive element.
Hence claim 12 will be deemed allowable if rewritten in an independent form.
Regarding claim 13, Ille teaches the invention set forth above. However, Ille does not particularly teach further comprising a resistive element coupled between the interconnection node and a gate of the second transistor.
Hence claim 13 will be deemed allowable if rewritten in an independent form.
Regarding claim 14, Ille teaches the invention set forth above. However, Ille does not particularly teach wherein a transistor of the stack has a gate, a source and a drain, wherein the gate is connected to the source via a resistive element.
Hence claim 14 will be deemed allowable if rewritten in an independent form.
Regarding claim 23, Ille teaches the invention set forth above. However, Ille does not particularly teach wherein the branch node connects the interconnection node to a gate of a transistor in the stack of transistors of the second branch.
Hence claim 23 will be deemed allowable if rewritten in an independent form.
Claims 7, 16-17, 19-21 and 25 are withdrawn.
Claims 11, 18 and 26 are cancelled.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/ Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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