DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al (US 2020/0036478) [R1]
For claim 1, R1 discloses a first wireless signal processing circuit (paragraphs 65, 97, 175-186, Fig. 7-13); a second wireless signal processing circuit (paragraphs 40-50, 97, 175-186, 279-282 Fig. 7-13); and a processor link management unit that configured to establish establishes a multilink with a wireless terminal apparatus using the first wireless signal processing circuit and the second wireless signal processing circuit (paragraphs 65, 97, 175-186, Fig. 7-13), wherein the processor link management unit is configured to generate generates a trigger frame for causing the wireless terminal apparatus to transmit uplink data, and cause causes each of the first wireless signal processing circuit and the second wireless signal processing circuit to transmit the trigger frame (paragraphs 65, 97, 175-186, Fig. 7-13 simultaneous, duplicate, etc trigger frames and actions).
For claim 5, R1 discloses a first wireless signal processing circuit (paragraphs 65, 97, 175-186, Fig. 7-13); a second wireless signal processing circuit ; and a processor link management unit that configured to establish establishes a multilink w(paragraphs 65, 97, 175-186, Fig. 7-13)ith a base station using the first wireless signal processing circuit and the second wireless signal processing circuit, wherein when receiving a trigger frame instructing transmission of uplink data from the base station (paragraphs 65, 97, 175-186, Fig. 7-13), the processor link management unit is configured to cause causes each of the first wireless signal processing circuit and the second wireless signal processing circuit to transmit the uplink data (paragraphs 65, 97, 175-186, Fig. 7-13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as anticipated by R1 or, in the alternative, under 35 U.S.C. 103 as obvious over R1.
For claims 2 and 6, R1 discloses in a case where the first wireless signal processing circuit and the second wireless signal processing circuit receive first uplink data and second uplink data in parallel (paragraphs 65, 97, 175-186, Fig. 7-13), the processor link management unit is configured to confirm confirms whether there is duplication between the first uplink data and the second uplink data, and when there is duplication, the processor link management unit is configured to output outputs one of the first uplink data and the second uplink data to an upper layer (paragraphs 65, 97, 175-186, Fig. 7-13). OR, in the alternative, Examiner takes Official Notice that the use of in a case where the first wireless signal processing circuit and the second wireless signal processing circuit receive first uplink data and second uplink data in parallel, the processor link management unit is configured to confirm confirms whether there is duplication between the first uplink data and the second uplink data, and when there is duplication, the processor link management unit is configured to output outputs one of the first uplink data and the second uplink data to an upper layer was common and well known in the art prior to the effective filing date. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the previous combination to use in a case where the first wireless signal processing circuit and the second wireless signal processing circuit receive first uplink data and second uplink data in parallel, the processor link management unit is configured to confirm confirms whether there is duplication between the first uplink data and the second uplink data, and when there is duplication, the processor link management unit is configured to output outputs one of the first uplink data and the second uplink data to an upper layer. The technical reasoning to combine would be to allow enough time for transmission of data, more efficient transmission, and design choice.
For claim 3, R1 discloses the processor link management unit is configured to set a cycle of transmitting the trigger frame to the wireless terminal apparatus in accordance with a transmission cycle of low latency data of the wireless terminal apparatus (paragraphs 65, 97, 175-186, Fig. 7-13). OR, in the alternative, Examiner takes Official Notice that the use of the processor link management unit is configured to set a cycle of transmitting the trigger frame to the wireless terminal apparatus in accordance with a transmission cycle of low latency data of the wireless terminal apparatus was common and well known in the art prior to the effective filing date. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the previous combination to use the processor link management unit is configured to set a cycle of transmitting the trigger frame to the wireless terminal apparatus in accordance with a transmission cycle of low latency data of the wireless terminal apparatus. The technical reasoning to combine would be to allow enough time for transmission of data, more efficient transmission, and design choice.
For claim 4, R1 discloses the processor link management unit is configured to cause each of the first wireless signal processing circuit and the second wireless signal processing circuit to transmit a beacon including information related to the transmission cycle of the trigger frame (paragraphs 65, 97, 175-186, Fig. 7-13).
For claim 7, R1 discloses bring each of the first wireless signal processing circuit and the second wireless signal processing circuit into a state capable of receiving a wireless signal on the basis of information related to a transmission cycle of the trigger frame received from the base station (paragraphs 65, 97, 175-186, Fig. 7-13). OR, in the alternative, Examiner takes Official Notice that the use of bring each of the first wireless signal processing circuit and the second wireless signal processing circuit into a state capable of receiving a wireless signal on the basis of information related to a transmission cycle of the trigger frame received from the base station was common and well known in the art prior to the effective filing date. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify R1 to use bring each of the first wireless signal processing circuit and the second wireless signal processing circuit into a state capable of receiving a wireless signal on the basis of information related to a transmission cycle of the trigger frame received from the base station. The technical reasoning to combine would be to allow enough time for transmission of data, more efficient transmission, and design choice.
For claim 8, R1 discloses the uplink data is low latency data, and the processor link management unit is configured to wait waits for transmission of the uplink data until the trigger frame is received (paragraphs 65, 97, 175-186, Fig. 7-13). OR, in the alternative, Examiner takes Official Notice that the use of the uplink data is low latency data, and the processor link management unit is configured to wait waits for transmission of the uplink data until the trigger frame is received was common and well known in the art prior to the effective filing date. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify R1 to use the uplink data is low latency data, and the processor link management unit is configured to wait waits for transmission of the uplink data until the trigger frame is received. The technical reasoning to combine would be to allow enough time for transmission of data, more efficient transmission, and design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Shimoda et al (US 2024/0276442) discloses transmission duplication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER R CROMPTON whose telephone number is (571)270-3678. The examiner can normally be reached 10AM-4PM ET M-Th.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Asad Nawaz can be reached at (571)272-3988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER R CROMPTON/Primary Examiner, Art Unit 2463
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