DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 recites the limitation “the signal input pin of the device”, “the reference clock incrementing the SCKCTR”. There is insufficient antecedent basis for these limitations in the claim. Clarification or correction is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 22 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 1 recites a TDC. Claim 22 recites a method of converting the timing of transition events. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7, 10-12, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 7,332,973).
Regarding claim 1, Lee et al. (Figs. 3-4) discloses a time to digital converter (TDC) (TDC 310/ TDC 320) comprising: a tapped delay line (TDL) (delay line 420; col. 8, lines 22-23) having two or more sectors (delay units 424), each sector of the two or more sectors having a dedicated or a shared latching clock (latching clock 314), or two or more TDLs (delay lines 420 of TDCs 310 and 320 of Fig. 4) each having at least one sector (424), wherein each TDL (delay line 420 of TDC 310 or TDC 320) of the two or more TDLs includes a dedicated latching clock (314 or 324) for each sector (424); and a snapshot register (latches 450 through 458) configured to latch each respective sector on its respective latching clock to generate respective thermometer readings (TDLSecSs) (col. 8, lines 40-53).
Regarding claim 2, Lee et al. (Figs. 3-4) discloses the TDC of claim 1 further comprising at least one encoder (encoder 460 of Fig. 4) configured to generate a numerical representation (TDLSecSE) of each of the thermometer readings (col. 9, lines 23-30), wherein each TDLSecSE is generated by encoding a location of a transition in a TDLSecS or between adjacent TDLSecSs (col. 8, lines 40-53).
Regarding claim 7, Lee et al disclose the TDC of claim 1 wherein a minimum time interval between two timestamps is equal or greater than a TDLSec time interval (col. 8, lines 15-25).
Regarding claim 10, Lee et al disclose the TDC of claim 1, wherein the TDC includes the two or more TDLs (420s) including a first TDL (420 of TDC 310) and a second TDL (420 of TDC 320), wherein a signal transition is captured on the first TDL, on the second TDL, or an overlapping section of the first and second TDL (captured by latches 450 through 458).
Regarding claim 11, Lee et al disclose the TDC of claim 1 wherein each TDL has a propagation delay shorter than a period of its respective latching clock (see, Fig. 5).
Regarding claim 12, Lee et al disclose the TDC of claim 11, wherein any signal transition is captured by a plurality of the TDLs (col. 8, lines 40-64).
Regarding claim 14, Lee et al disclose the TDC of claim 1 further comprising a raw counter (counter 440 of Fig. 4) of a first latching clock or a raw counter (counter 440 of Fig. 4) of a second latching clock (312/314) or both or an additional software counter for either or both the raw counters wherein the raw counter wraps around and provides and provides a dynamic range equal with a maximum count number.
Regarding claim 15, Lee et al disclose the TDC of claim 1 wherein a shortest detectable signal pulse is a propagation time of a signal through a TDLSec (col. 9, lines 1-15).
Allowable Subject Matter
Claims 3-6, 8-9, 13, 16-21, and 23-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3-4 and 6, Lee et al. does not disclose the TDC of claim 1 “further
comprising one or more adders, wherein the one or more adders are configured to generate a timestamp (TDLSecTS) for each respective TDLSecSE by adding a delay (PhOff) to each respective TDLSecSE, wherein the delay is relative to a common reference”.
Regarding claim 5, Lee et al. does not disclose the TDC of claim 2, “where encoding comprises:
a. calculating a sum of all bits of the TDLSecSs; and
b. if the sum is different from a compact sum which is either null or equal with a total number of bits of TDLSecS, and
i. the sum of a first plurality of bits near the signal entry to the TDLSecS is bigger than the sum of a second plurality of bits at the opposite end of the TDLSecS, then TDLSecSE referenced from the end point of signal entry to TDLSecS is valid and is equal with the sum, and the transition is a rising edge, or
ii. the sum of a first plurality of bits near the end point of signal entry to the TDLSecS is smaller than the sum of a second plurality of bits at the opposite end of the TDLSecS then TDLSecSE, referenced from the signal entry endpoint of TDLSecS is valid and is equal with the difference between the number of bits in the TDLSecS and the sum, and the transition is a falling edge; or
c. if the sum of TDLSecS is compact and not null and the sum of an adjacent TDLSecS connected at the output of theTDLSecS is compact and null then the TDLSecSE referenced from the end point of signal entry of TDLSecS is the total number of bits of TDLSecS, and the transition is valid and is positive,
d. if the sum of TDLSecS is compact and null and the sum of an adjacent TDLSecS connected at the output of theTDLSecS is compact and not null then the TDLSecSE referenced from the end point of signal entry of TDLSecS is the total number of bits of TDLSecS and the transition is negative, or
e. if the sum of TDLSecS is compact and the sum of an adjacent TDLSecS connected at the output of theTDLSecS is also compact and both sums are equal TDLSecSE is not valid”.
Regarding claim 8, Lee et al. does not disclose the TDC of claim 1 “further comprising:
a) a first snapshot subsystem comprising:
i. a first TDL connected to an event signal and latched into a first snapshot register by a first clock,
ii. a second clock with a known, deterministic relation to the first clock, and
iii. the second TDL connected to the event signal and latched into a second snapshot register by the second clock; and
b) a second snapshot subsystem comprising:
iv. a third TDL connected to the event signal and latched into a third snapshot register by the first clock, and
v. a fourth TDL connected to the event signal and latched into a fourth snapshot register by the second clock; and
c) a logic block generating timestamps from data collected in the four snapshot registers from both snapshot subsystems”.
Regarding claim 9, Lee et al. does not disclose the TDC of claim 1 the TDC of claim 1 “further comprising a logic block further comprises:
a processing unit configured to perform either:
an average of a tap delay of a signal transition in a time overlapping section at one end of the first snapshot register with a tap delay of a signal transition in the time overlapping section at the other end of the second snapshot register, or
a selection among the tap delay of a signal transition signal in the time overlapping section at one end of the first snapshot register and the tap delay of a signal transition signal in the time overlapping section at the other end of the second snapshot register”.
Regarding claim 13, Lee et al. does not disclose the TDC of claim 13 “wherein the TDC is configured to:
measure FPGA hardware and select TDL taps and associated routing to latching registers for a preselected FPGA CARRY chain, or
select, from a plurality of FPGA CARRY chains, a subset of the plurality of FPGA CARRY chains having TDL taps distributions, wherein the delay between consecutive TDL taps of the subset of FPGA CARRY chains or preselected FPGA CARRY chain is similar or equal”.
Regarding claim 16, Lee et al. does not disclose the TDC of claim 1, “wherein the TDC is configured to measure a respective delay of each TDL tap through a calibration process”.
Regarding claim 17, Lee et al. does not disclose the TDC of claim 1, “wherein the TDC is further configured to convert a TDL tap number of a transition into a propagation delay from an input of a sector to the TDL tap”.
Regarding claim 18, Lee et al. does not disclose the TDC of claim 1 “wherein the TDC is further configured to measure a relative propagation delay offset (PhOff) between a common signal reference point and the first TDL tap of each TDL”.
Regarding claims 19-20, Lee et al. does not disclose the TDC of claim 1 “further configured to disambiguate a signal transition, wherein disambiguating the same signal event in a time overlapping section of two adjacent TDLSec, includes:
a. determining the start and ending tap number or time of the overlapping section of two time adjacent TDLSec by identifying a range where same polarity transition is detected on both TDLSecs,
b. converting the transition (TDLSecSE) from one of the TDLSec to the other TDLSec by adding a time constant or subtracting another time constant, and
c. adding or averaging the two TDLSecSE at the same TDLSec”.
Regarding claim 21, Lee et al. does not disclose the TDC of claim 1, “wherein the TDC is further configured to retime the TDLSecS or TDLSecSE captured by one of the TDL with a second clock, to become contemporaneous to a time domain of a first clock”.
Regarding claims 23-24, Lee et al. does not disclose the TDC of claim 1 “wherein the TDC is further configured to perform a calibration and measure of a sector through a sweeping wave comprising by:
a. selecting a Phase Progression constant, representing the precision of the measurement, and
i. generating a signal with a period determined by the period of the first clock modified by the Phase Progression; or
b. generating a signal with a period close to the first clock, and
i. determining the Phase Progression by counting a first number of periods of the first clock between transitions of same polarity of the same tap of the sector, and dividing the period of the first clock by the first number of periods; and
c. determining the delay of a tap by counting a second number of periods of the first clock between a transition of the first tap of and a transition of the second tap, and d. multiplying the second number of periods with the phase progression”.
Regarding claim 25, Lee et al. does not disclose the TDC of claim 1, “further comprising a LUT to linearize, or convert tap numbers to a time delay of the tap number for the positive edge or for the negative edge of the event signal, or for both”.
Regarding claim 26, Lee et al. does not disclose the TDC of claim 1, “further implementing a pseudo differential logic to mitigate noise, wherein the logic inverts the signal polarity for half of the TDL inputs of an ETDC and restores the original polarity by inverting the TDLSecS”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon E. Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAI M NGUYEN/Primary Examiner, Art Unit 2845