DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-12 are objected to because of the following informalities:
In claim 1, line 4, it is suggested that the “comprising” be replaced with “comprising:”.
In claim 1, line 12, it is suggested that the “wherein processing comprises estimation of the cross factor” be replaced with “wherein the processing comprises estimation of a cross factor”.
In claim 1, line 13, it is suggested that the “wherein processing” be replaced with “wherein the processing”.
Claims 2-12 are depending on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jana et al. (US 2019/0245718 A1).
Consider claim 1:
Jana discloses a method for receiving first and second digital signals (see Fig. 3A and paragraphs 0029-0031, where Jana describes a receiver 250 which includes an interference mitigation apparatus 280, the interference mitigation apparatus 280 receives two digital signals from ADC 2621 and ADC 2622), comprising first and second independent streams of oversampled and pulse-shaped baseband digital complex-valued samples (see Fig. 3A and paragraphs 0029-0032, where Jana describes that the ADC 2621 is included in a first branch 2521 and the ADC 2622 is included in a second branch 2522, the ADC 2621 and the ADC 2622 have sampling rate faster than Nyquist sampling rate, a matched filtering block 2601 applies a complex pulse shape on down-converted signal from AFE 2561 , and a matched filtering block 2602 applies a complex pulse shape on down-converted signal from 2562), in a dual-polarization digital communication system utilizing first and second radio-frequency (RF) polarization channels (see Fig. 3A and paragraphs 0028-0030, where Jana describes that the ADC 2621 and ADC 2622 receive signals transmitted through a horizontally polarized antenna 221 and a vertically polarized antenna 222), comprising:
receiving the two digital signals transmitted via the two radio-frequency (RF) polarization channels (see Fig. 3A and paragraphs 0028-0031, where Jana describes that the interference mitigation apparatus 280 receives the two digital signals through the horizontally polarized antenna 221 and the vertically polarized antenna 222),
wherein each of the two received digital signals comprises a stream of oversampled and pulse-shaped baseband digital complex-valued samples (see Fig. 3A and paragraphs 0029-0032, where Jana describes that the ADC 2621 and the ADC 2622 have sampling rate faster than Nyquist sampling rate, a matched filtering block 2601 applies a complex pulse shape on the down-converted signal from AFE 2561 , and a matched filtering block 2602 applies a complex pulse shape on the down-converted signal from 2562), and
wherein each of the two received digital signals also includes a cross-polarization interference (XPI) component (see Fig. 3A and paragraph 0029, where Jana describes the first branch 2521 receives a strong component of the horizontally polarized signal and a weaker component of the vertically polarized signal, due to cross-polarization interference; see Fig. 3A and paragraph 0032, where Jana describes the second branch 2522 receives a strong component of the vertically polarized signal and a weaker component of the horizontally polarized signal, due to cross-polarization interference),
jointly processing the two received digital signals for providing estimation and cancellation of the cross-polarization interference (XPI) components (see Fig. 4 and paragraphs 0037-0039, where Jana describes that the interference mitigation apparatus 280 receives the two digital signals u1 and u2 from the ADC 2621 and the ADC 2622 , a XPI mitigation module 410 generates cross-polarization interference components b1 and b2 based on the received two digital signals u1 and u2 ),
wherein processing comprises estimation of the cross factor (see Fig. 4 and paragraphs 0038-0039, where Jana describes that the interference mitigation apparatus 280 generates two symbol estimates a1 and a2 for cross polarization mitigation), and
wherein processing further comprises estimation of each interfering component by means of the estimated cross factor and subtraction of each estimated interfering component from the corresponding received signal (see Fig. 4 and paragraphs 0037-0038, where Jana describes that the XPI mitigation module 410 generates the cross-polarization interference components b1 and b2 based on the two symbol estimates a1 and a2 , and the cross-polarization interference components b1 and b2 are subtracted from the two digital signals z1 and z2 which are phase corrected and filtered versions of the received two digital signals u1 and u2).
Consider claim 2:
Jana discloses the method according to claim 1 above. Jana discloses: the method is applicable in a dual-channel receiver device for any digital communication system both for forward and return links (see Fig. 1 and paragraphs 0021-0022, where Jana describes that the receiver is configured in a dual-polarization communication system using two receiving channels).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jana et al. (US 2019/0245718 A1), as applied to claim 1 above, and further in view of Henttu (US 2004/0071103 A1).
Consider claim 3:
Jana discloses the method according to claim 1 above. Jana does not specifically disclose: buffering the received samples of the first and second channels, in order to construct first and second vectors of consecutive samples of the first and second digital signals, respectively, with the two vectors having the equal even-number length (N), wherein the length (N) is the number of consecutive samples.
Henttu teaches: buffering received samples of a first and second channels, in order to construct first and second vectors of consecutive samples of first and second digital signals, respectively, with the two vectors having the equal even-number length (N), wherein the length (N) is the number of consecutive samples (see Fig. 5 and paragraph 0043, where Henttu describes a method of attenuating interference in a receiver of a wideband telecommunication system, the received signal samples 500 are stored at a first sample vector 504 sequentially and a second sample vector 506 sequentially, the first sample vector 504 has a length of 8 and the second sample vector 506 also has a length of 8; see paragraph 0030, where Henttu describes that the samples are stored in a buffer memory).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: buffering the received samples of the first and second channels, in order to construct first and second vectors of consecutive samples of the first and second digital signals, respectively, with the two vectors having the equal even-number length (N), wherein the length (N) is the number of consecutive samples, as taught by Henttu to modify the method of Jana in order to treat the samples block-specifically, as discussed by Henttu (see paragraph 0043).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jana et al. (US 2019/0245718 A1), as applied to claim 1 above, and further in view of Mazumder et al. (US 11,526,453 B1).
Consider claim 4:
Jana discloses the method according to claim 1 above. Jana does not specifically disclose: a main clock signal, determining the fundamental frequency of the processing, an odd clock signal, being half the frequency of the main clock signal, having its rising edge synchronous with the rising edge of the main clock signal, and an even clock signal, being a shifted version of the odd clock signal, having its rising edge synchronous with the falling edge of the main clock signal.
Mazumder teaches: a main clock signal, determining the fundamental frequency of the processing (see Fig. 3A and col. 9, lines 54-65, where Mazumder describes a clock signal CLK), an odd clock signal, being half the frequency of the main clock signal, having its rising edge synchronous with the rising edge of the main clock signal (see Fig. 3A and col. 9, lines 54-65, where Mazumder describes a clock signal DLL0 which has a frequency that is half the frequency of the clock signal CLK, the rising edge of the clock signal DLL0 is at the same time as the rising edge of the clock signal CLK), and an even clock signal, being a shifted version of the odd clock signal, having its rising edge synchronous with the falling edge of the main clock signal (see Fig. 3A and col. 9, lines 54-65, where Mazumder describes a clock signal DLL90 which is a 90 degree shift of the clock signal DLL0, the rising edge of the clock signal DLL90 is at the same time as the falling edge of the clock signal CLK).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a main clock signal, determining the fundamental frequency of the processing, an odd clock signal, being half the frequency of the main clock signal, having its rising edge synchronous with the rising edge of the main clock signal, and an even clock signal, being a shifted version of the odd clock signal, having its rising edge synchronous with the falling edge of the main clock signal, as taught by Mazumder to modify the method of Jana in order to coordinate delivery timing, as discussed by Mazumder (see col. 2, lines 19-20).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jana et al. (US 2019/0245718 A1) in view of Mazumder et al. (US 11,526,453 B1), as applied to claim 4 above, and further in view of Henttu (US 2004/0071103 A1) and Jonnalagadda (US 2004/0128578 A1).
Consider claim 5:
Jana in view of Mazumder discloses the method according to claim 4 above. Jana and Mazumder do not specifically disclose: (1), sequentially feeding the received samples of the first and second channels into first and second shift registers with equal even-number length (const_length_of_reg_1), and (2) each shift register comprises delay elements, wherein the length (const_length_of_reg_1) is the number of delay elements, and wherein the shift registers are driven by the main clock signal.
Regarding (1), Henttu teaches: sequentially feeding the received samples of the first and second channels into first and second shift registers with equal even-number length (const_length_of_reg_1) (see Fig. 5 and paragraph 0043, where Henttu describes that received signal samples 500 are stored at a first sample vector 504 sequentially and a second sample vector 506 sequentially, the first sample vector 504 has a length of 8 and the second sample vector 506 also has a length of 8; see paragraph 0030, where Henttu describes that the samples are stored in a buffer memory).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: sequentially feeding the received samples of the first and second channels into first and second shift registers with equal even-number length (const_length_of_reg_1), as taught by Henttu to modify the method of Jana and Mazumder in order to treat the samples block-specifically, as discussed by Henttu (see paragraph 0043).
Regarding (2), Jonnalagadda teaches: each shift register comprises delay elements, wherein the length (const_length_of_reg_1) is the number of delay elements, and wherein the shift registers are driven by a main clock signal (see Fig. 4A and paragraph 0073, where Jonnalagadda describes a shift register 450 that includes a number of D flip-flops, each D flip-flop is a delay element to store one sample, the D flip-flops are driven by a clock signal 425-1).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: each shift register comprises delay elements, wherein the length (const_length_of_reg_1) is the number of delay elements, and wherein the shift registers are driven by the main clock signal, as taught by Jonnalagadda to modify the method of Jana and Mazumder in order to operate at high frequency, as discussed by Jonnalagadda (see paragraph 0072).
Allowable Subject Matter
Claims 6-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/LIHONG YU/ Primary Examiner, Art Unit 2631