DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sandstrom et al. USPGPUB 2010/0099051 (hereinafter “Sandstrom”) in view of .
As to claim 1, Sandstrom teaches a non-transitory medium holding computing device-executable instructions for performing 3D photoresist profile generation (paragraph 0006-0008 and FIG. 7, 26 and 29), the instructions when executed causing at least one computing device equipped with at least one processor (paragraph 0225-0227) to: receive in a virtual fabrication environment a top contour mask that describes a photoresist profile at a top of a semiconductor device structure being fabricated and a bottom contour mask that describes a photoresist profile at a bottom of a semiconductor device structure being fabricated (paragraph 0067 and paragraph 0070-0076); creating a loading map using a subset of density information extracted from the top contour mask and the bottom contour mask (paragraph 0008-0010 and 0227-0228); perform an etch operation using the loading map to generate a 3D photoresist profile for the semiconductor device structure (paragraph 0213-0216 and 0227 and FIG. 26-29).
Sandstrom does not explicitly teach output a result of the etch operation.
However, Kooiman teaches output a result of the etch operation (paragraph 0072-0076 and 0094).
Sandstrom and Kooiman are analogous art because they are from the same field of endeavor and contain overlapping structural and functional similarities. They both relate to semiconductor system.
Therefore at the time of effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the above semiconductor system, as taught by Reynolds, and incorporating result of the etch operation, as taught by Kooiman.
One of ordinary skill in the art would have been motivated to improve monitoring, controlling several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate, as suggested by Kooiman (paragraph 0003).
As to claims 2, 10 and 18, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Sandstrom further teaches wherein the creation of the loading map also uses contour edge information extracted from the top contour mask and the bottom contour mask (paragraph 0197-0198 and FIG. 21-29).
As to claims 3, 11 and 19, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Sandstrom further teaches wherein the instructions when executed cause the at least one computing device to: receive in the virtual fabrication environment at least one additional contour mask at a depth in the semiconductor device structure being fabricated that is located between the top contour mask and bottom contour mask; and create the loading map by also using contour edge information extracted from the at least one additional contour mask (paragraph 0067-0069 and 0197, FIG. 21-29).
As to claim 4, 12 and 20, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Sandstrom further teaches wherein the instructions when executed cause the at least one computing device to: perform linear interpolation for square corner polygon shapes located on one or more of the top contour mask and the bottom contour mask, to insert additional edge data points (paragraph 0197-0203 and FIG. FIG. 26-29).
As to claims, 5 and 13, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Sandstrom further teaches wherein the instructions when executed cause the at least one computing device to: generate a first density map by examining a subset of locations in the top contour mask; generate a second density map by examining a subset of locations in the bottom contour mask; and combine the first density map and second density map into a single map holding the subset of density information used to create the loading map (paragraph 0207-0213 and FIG. 26-29).
As to claims 6 and 14, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Sandstrom further teaches wherein the instructions when executed cause the at least one computing device to: provide a user interface configured to receive a user-selected speed parameter controlling the size of the subset of density information extracted from top contour mask and the bottom contour mask (paragraph 0136-0137 and FIG. 15).
As to claims 7 and 15, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Sandstrom further teaches wherein the instructions when executed cause the at least one computing device to: provide a user interface configured to receive a user-selected interpolation parameter indicating a type of interpolation method used to create the loading map (paragraph 0203-0207).
As to claims 8 and 16, Sandstrom and Kooiman teaches all the limitations of the base claims as outlined above.
Kooiman further teaches wherein the instructions when executed cause the at least one computing device to: provide a user interface configured to receive a user-selected polarity parameter (paragraph 0074-0086).
As to claim 9, is related to claim 1, with similar limitations also rejected by same rational.
As to claim 17, is related to claim 1, with similar limitations also rejected by same rational.
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The prior art made of record and listed on the attached PTO Form 892 but not relied upon is considered pertinent to applicant's disclosure.
Okumura USPGPUB 20050087853 A1 teaches a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention comprises a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure. A dielectric film formed between the first substrate and the wiring structure may be an adhesive layer..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZIAUL KARIM whose telephone number is (571)270-3279. The examiner can normally be reached on Monday-Thursday 8:00-4:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mohammad Ali can be reached on 571 272 4105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZIAUL KARIM/Primary Examiner, Art Unit 2119
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