DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed on 08/26/2024.
Claims 1-16 are pending.
Drawings
The drawings are objected to because there are minor informalities. In FIG 7, element 700 is not labeled or mentioned in the specification. In FIG 8, 804 is not labeled. Examiner recommends labeling 804 as “Bus”. Also, in FIG 8, “Input protion” is misspelled. Examiner recommends changing this to “Input portion”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: The use of the word “in the bellow” in paragraphs 53, 63, 72, 85, 101, and 107 is incorrect. Examiner recommends the applicant should chang the expression to “According to the following”. Software queue “11161” should be “21161”, hardware queue “11171” should be “21171” [0066], General block layer “1116” should be “21116” [0070], An offloading card “5022” should be “502” [0103].
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “an offloading card” that performs functional limitations and is not modified by structure. in claims 1-5 and “a controller” in claims 3-5.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. A review of the disclosure as originally filed, hereafter “disclosure”, reveals that the corresponding structure of the “offloading card” and “controller” are a general purpose computer, see at least instant specification [0024]. In accordance with 2181(||)(B), when the corresponding structure of computer implemented mean plus function limitations corresponds toa general purpose computer, an algorithm is required to transform the general purpose computer into a special purpose computer to be sufficient as corresponding structure. Upon further review of the disclosure, Applicant has failed to define the algorithm for each of the claimed functions and has instead only provided either verbatim support for the claimed function (which is insufficient as a steps of steps of a corresponding algorithm) or exemplary language that does not make clear the metes and bounds of the algorithm. As such, see rejections under 35 U.S.C. 112(a) and (b) below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
he specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1-5, 9, and 12 recite a “offloading card” which invokes 35 U.S.C. 112(f), see claim interpretation above. The disclosure does not recite sufficient corresponding structure (in this instance computer + algorithm), again see claim interpretation above. As such, and in accordance with MPEP 2181(||)(B), last paragraph “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a).”
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 9, 10, 12, 15, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-5 limitations “offloading card" and "controller” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure fails to disclose sufficient corresponding structure (in this instance computer + algorithm), see claim interpretation above. As such, and in accordance with MPEP 2181(||)(B), " For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b)". Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
With regard to Claims 4, 9, and 12the claims recite that “the applications are executed by corresponding cores”, but do not clearly define the correspondence between the applications and the processor cores.
With regard to Claims 5, 10, and 12the claims recite that the “NVMe controller transfers the input/output request to the offloading card”. The NVMe controller is itself recited as being part of the offloading card. It is therefore unclear what component or interface within the offloading card is intended to receive the input/output request. Claims 5, 10, and 12 are further rejected under 35 U.S.C. 112(b) as being indefinite because the claims recite a single input/output request issued by an application but transfer that request via “the hardware queues corresponding to the created namespaces”. It is unclear whether the single input/output request is transferred through multiple hardware queues or through the particular hardware queue corresponding to the namespace associated with that application.
With regard to claims 5, 10, and 15-16, they depend from rejected claims and do not resolve the deficiencies thereof and are therefore additionally rejected for the same reasons as above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 and 12-16 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-5 are directed to a system and falls within the statutory category of machines; Claims 6-10, and 12 are directed to methods and fall within the statutory category of processes; Claims 13 and 15 are directed to an electronic device and falls within the statutory category of machines; Claims 14 and 16 are directed to a computer-readable media and falls within the statutory category of articles of manufacture. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1, 6, 13, and 14: The limitations “the offloading card creates corresponding multiple namespaces for the multiple applications according to the namespace creation request, and the offloading card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues respectively to the corresponding namespaces”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate creating namespaces for multiple applications according to a request, as well as allocate and bind queues to namespaces according to a request.
Therefore, Yes, claim 1 recites judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 1, 6, 13, and 14: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional elements – “a host and the offloading card connected to the host”, “An electronic device, comprising a memory and a processor; wherein the memory is configured to store one or more pieces of computer instructions, the one or more pieces of computer instructions are executed by the processor to implement steps of the method according to claim 6.” as well as “A non-transitory readable storage medium, storing computer instructions, wherein when the computer instructions are executed by a processor, steps of the method according to claim 6 are implemented.” which are merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claim 1 recites the following additional elements – “wherein the host has multiple applications issuing an input/output request running thereon” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Moreover, claim 1 recites the following additional elements – “and the host sends a namespace creation request to the offloading card” which is merely a recitation of insignificant extra-solution data transmission activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application. These limitations will be further addressed below at Step 2B as also being Well-understood, Routine, and Conventional (WURC). Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that the claim 1 not only recites a judicial exception but that the claim is directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B: Claims 1, 6, 13, and 14: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and field of use/technological environment which do not amount to significantly more than the abstract idea. Moreover, this insignificant extra-solution of data transmission is WURC, see (MPEP 2106.05(d)(||) “The courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory”.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1, 6, 13, and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claims 2 and 7, they recite “wherein the host has a virtual machine running thereon, the multiple applications run in the virtual machine, and the virtual machine comprises:” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Further, claims 2 and 7 recite “a driver, configured to manage the multiple hardware queues,” which a merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)). Moreover, claims 2 and 7 recite “wherein the virtual machine sends the namespace creation request to the offloading card via the driver.” which is merely a recitation of insignificant extra-solution data transmission activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application. Moreover, this insignificant extra-solution of data transmission is WURC, see (MPEP 2106.05(d)(||) “The courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory”, and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2 and 7 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 2 and 7 do not recite patent eligible subject matter under 35 U.S.C. § 101.With regard to claims 3 and 8, they recite additional abstract idea recitations of “wherein, the controller creates respective namespaces for the multiple applications according to the namespace creation request, allocates the multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues respectively to the corresponding namespaces.” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate creating namespaces for multiple applications according to a request, as well as allocate and bind queues corresponding to created namespaces from the accelerator. Further, claims 3 and 8 recite “wherein the offloading card comprises a controller and a hardware accelerator” which a merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 3 and 8 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 3 and 8 do not recite patent eligible subject matter under 35 U.S.C. § 101.With regard to claims 4 and 9, they recite additional abstract idea recitations of “and establishes a one-to-one corresponding relationship from the multiple software queues to the multiple hardware queues.” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate a one-to-one relationship from one queue to another queue. Further, claims 4 and 9 recite “wherein the host comprises a central processing unit with multiple cores, the virtual machine comprises a user space and a kernel space” as well as “and wherein the kernel space comprises a general block layer and the driver, the general block layer comprises multiple software queues corresponding to the multiple cores” which a merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Moreover, claims 4 and 9 recite “wherein the user space has the multiple applications running therein, the applications are executed by corresponding cores” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 4 and 9 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 4 and 9 do not recite patent eligible subject matter under 35 U.S.C. § 101.With regard to claims 5 and 10, they recite additional abstract idea recitations of “wherein the input/output request is converted into an input/output request conforming with an NVMe protocol by processing of the general block layer and the NVMe driver” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate converting an I/O request from one protocol to another. Further, claims 5 and 10 recite “wherein the driver is ana Non-Volatile Memory Host Controller Interface Specification (NVMe) driver, the controller is an NVMe controller, wherein the host is connected to an NVMe device via the offloading card, wherein the NVMe device is mounted inside the virtual machine” which is merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claims 5 and 10 recite “wherein an application running in the user space” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Moreover, claims 5 and 10 recite “issues an input/output request to the general block layer”, “and the input/output request conforming with the NVMe protocol is sent to the NVMe controller, wherein the NVMe controller transfers the input/output request conforming with the NVMe protocol to the offloading card via the hardware queues corresponding to the created namespaces, wherein the offloading card sends the input/output request conforming with the NVMe protocol to the NVMe device.” which are merely a recitation of insignificant extra-solution data transmission activity (see MPEP § 2106.05(g)). Moreover, this insignificant extra-solution of data transmission is WURC, see (MPEP 2106.05(d)(||) “The courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory”, and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 5 and 10 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 5 and 10 do not recite patent eligible subject matter under 35 U.S.C. § 101.With regard to claims 12, 15, and 16, they recite additional abstract idea recitations of “the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request, allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues respectively to the corresponding namespaces” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate creating namespaces for multiple applications according to a request, as well as allocate and bind queues corresponding to created namespaces from the accelerator. Furthermore, “the general block layer establishes a one-to-one correspondence relationship from the multiple software queues to the multiple hardware queues” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate a one-to-one relationship from one queue to another queue. Moreover, “converting, by processing of the general block layer and the NVMe driver, the input/output request into an input/output request conforming with NVMe protocol” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate converting an I/O request from one protocol to another. Further, claims, 12, 15 and 16 recite “wherein the method runs in a system for processing an input/output request, the system for processing the input/output request comprises a host, an offloading card, and ana Non-Volatile Memory Host Controller Interface Specification (NVMe) device connected to the host via the offloading card, wherein the host has a virtual machine running thereon, the host comprises a central processing unit with multiple cores, the virtual machine comprises a user space and a kernel space”, “the applications are executed by corresponding cores, the kernel space comprises a general block layer and an NVMe driver, the general block layer comprises multiple software queues corresponding to the multiple cores,”, “wherein the NVMe driver is configured to manage the multiple hardware queues”, “An electronic device, comprising a memory and a processor; wherein the memory is configured to store one or more pieces of computer instructions, the one or more pieces of computer instructions are executed by the processor to implement steps of the method according to claim 12.”, “A non-transitory readable storage medium, storing computer instructions, wherein when the computer instructions are executed by a processor, steps of the method according to claim 12 are implemented.” which are merely recitations of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claim 12 recites “wherein the user space has multiple applications issuing an input/output request running therein” which is merely a recitation of a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into practical application. Moreover, claim 12 recites “the virtual machine sends a namespace creation request to the offloading card via the NVMe driver, wherein the offloading card comprises an NVMe controller and a hardware accelerator”, “wherein the method further comprises: issuing, by an application running in the user space, an input/output request to the general block layer;”, “and sending the input/output request conforming with the NVMe protocol to the NVMe controller; transferring, by the NVMe controller, the input/output request conforming with the NVMe protocol to the offloading card via the hardware queues corresponding to the created namespaces; and sending, by the offloading card, the input/output request conforming with the NVMe protocol to the NVMe device.” which are merely a recitation of insignificant extra-solution data transmission activity (see MPEP § 2106.05(g)). Moreover, this insignificant extra-solution of data transmission is WURC, see (MPEP 2106.05(d)(||) “The courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity i. Receiving or transmitting data over a network…iv. Storing and retrieving information in memory”, and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 12, 15 and 16 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 12, 15, and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang Pub. No. CN 111198663 A (hereafter Yang), citations correspond to English translation provided herewith, in view of Hussain et al. Pub. No. US 2015/0317088 A1 (hereafter Hussain).
With regards to claim 1, Yang teaches a system for managing a namespace of an offloading card, comprising a host and the offloading card connected to the host, wherein (The storage offloading card 200 connects to an NVMe-compliant solid-state drive via a PCIe (Peripheral Component Interconnect express) bus, and the storage offloading card connects to the server via a PCIe bus. [0058]), the host has multiple applications issuing an input/output request running thereon, and the host sends a namespace creation request to the offloading card, the offloading card creates corresponding multiple namespaces for the multiple applications according to the namespace creation request, (the server can send instructions to the storage offload card to execute the virtual functions loaded by the multiple virtual machines installed in the operating system. When the storage offload card receives the instructions, it can create namespaces corresponding to each virtual function in the solid-state drive for the implementation of the virtual functions and perform data access operations in the namespaces. The data access operations performed in each namespace are related to the virtual function corresponding to that namespace. [0060])Yang does not teach allocating and binding corresponding hardware queues to the created namespaces.However, in analogous art, Hussain teaches and the offloading card allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues respectively to the corresponding namespaces. (the hardware resource management scheme in the HW is manifested as the management port of the NVMe SSD, which is responsible for the initialization, resource configuration and allocation of queues and namespaces of the NVMe SSD...after the PF/VF is uniformly bound with the namespace and queue resources through a specific binding mechanism [0143]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the VM-specific NVMe namespace and hardware queue features of Hussain with the namespace creation features of Yang resulting in each namespace having dedicated queue resources through with I/O for that namespace can be independently processed.A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].
With regards to claim 6, Yang teaches a method for managing a namespace of an offloading card, wherein the method runs in a system for managing namespace of an offloading card, and the system for managing the namespace of the offloading card comprises a host and the offloading card connected to the host, wherein the method comprises: (The storage offloading card 200 connects to an NVMe-compliant solid-state drive via a PCIe (Peripheral Component Interconnect express) bus, and the storage offloading card connects to the server via a PCIe bus. [0058])sending, by the host, a namespace creation request to the offloading card, based on multiple applications issuing an input/output request running on the host; creating, by the offloading card, corresponding multiple namespaces (the server can send instructions to the storage offload card to execute the virtual functions loaded by the multiple virtual machines installed in the operating system. When the storage offload card receives the instructions, it can create namespaces corresponding to each virtual function in the solid-state drive for the implementation of the virtual functions and perform data access operations in the namespaces. The data access operations performed in each namespace are related to the virtual function corresponding to that namespace. [0060])Yang does not teach allocating and binding corresponding hardware queues to the created namespaces.However, in analogous art, Hussain teaches allocating, by the offloading card, multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binding the allocated multiple hardware queues respectively to the corresponding namespaces. (the hardware resource management scheme in the HW is manifested as the management port of the NVMe SSD, which is responsible for the initialization, resource configuration and allocation of queues and namespaces of the NVMe SSD...after the PF/VF is uniformly bound with the namespace and queue resources through a specific binding mechanism [0143]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the VM-specific NVMe namespace and hardware queue features of Hussain with the namespace creation features of Yang resulting in each namespace having dedicated queue resources through with I/O for that namespace can be independently processed.A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].
With regards to claim 13, Yang teaches an electronic device, comprising a memory and a processor; wherein the memory is configured to store one or more pieces of computer instructions, the one or more pieces of computer instructions are executed by the processor to implement steps of the method according to claim 6. (embodiments of the present invention provide an apparatus for controlling data access operations, the apparatus including a memory and a processor; Memory is used to store computer-readable instructions; The processor is used to read computer-readable instructions to perform the following operations [0030]-[0032])
With regards to claim 14, Yang teaches a non-transitory readable storage medium, storing computer instructions, wherein when the computer instructions are executed by a processor, steps of the method according to claim 6 are implemented. (a storage medium comprising a stored program, wherein the program is executed by a processor to perform the method described in any of the above embodiments. [0097])
Claims 2, 3, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang Pub. No. CN 111198663 A (hereafter Yang), citations correspond to English translation provided herewith, in view of Hussain et al. Pub. No. US 2015/0317088 A1 (hereafter Hussain) as applied to claims 1, 6, 13, and 14 above and in further view of Yoshida Pub. No. US 2021/0042246 A1 (hereafter Yoshida).
With regards to claim 2, Yang and Hussain teach the namespace management system of claim 1 using application-specific namespaces and corresponding hardware queues.Hussain further teaches wherein the host has a virtual machine running thereon, the multiple applications run in the virtual machine and the virtual machine comprises: a driver ( each of the VMs 110 running on the host 106 has an NVMe driver 114 configured to interact with the physical NVMe controller 102 and the virtual NVMe controllers 104 via the PCIe/NVMe link/connection 111. [0026])configured to manage the multiple hardware queues (When transmitting commands and/or data to and/or from a VM 110, the corresponding VF NVMe driver 114 directly puts and/or retrieves the commands and/or data from its queues and/or the data buffer, which is sent out or received from the PCIe/NVMe link/connection 111 without the data being accessed by the host 106 or any other VMs 110 running on the same host 106. [0027])Yang and Hussain do not teach that the namespace creating request itself is sent via the driver.However, in analogous art, Yoshida teaches wherein the virtual machine sends the namespace creation request to the offloading card via the driver (The application program 201A (or 201B) calls the library 401 using a function call for requesting the creation of the I/O submission queue, thereby requesting the library 401 to transmit an I/O submission queue creation request to the kernel 302 [0126]. the driver 304 of the kernel 302 executes an operation of storing the I/O submission queue creation request in the admin submission queue 601 and an operation of notifying the SSD 3 that a new management request…is stored in the admin submission queue 601 [0129]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the submission queue creation request transmitted through the driver of Yoshida with the VM/driver architecture of Hussain and the offloading card architecture of Yang resulting in the VM sending the submission queue creation request to the offloading card via the driver. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of ensuring that even when a delay in I/O processing with respect to one namespace occurs, a delay in I/O processing with respect to the other namespace can be prevented in at least Yoshida [0147].
With regards to claim 3, Yang, Hussain, and Yoshida teach the namespace-management system of claim 2 using VM-based applications, a driver, and namespace specific hardware queues. Hussain further teaches wherein the offloading card comprises a controller and a hardware accelerator (Each VF shares one or more physical resources on the physical NVMe controller 102, wherein such resources include but are not limited to on-controller memory, hardware accelerator and storage interface 118 of the physical NVMe controller 102. [0017]. The hardware implementation includes at least an NVMe processing engine 202, and an NVMe Queue Manager (NQM) 204 implemented to support the NVMe processing engine 202. the NQM 204 manages at least a submission queue 212...and a completion queue 214 [0018]).wherein the controller creates respective namespaces for the multiple applications according to the namespace creation request (a plurality of virtual NVMe controllers are created on a single physical NVMe controller...and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller. [0011])allocates the multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues respectively to the corresponding namespaces. (each of the virtual NVMe controllers 104 has one or more pairs of submission queue 212 and completion queue 214 associated with it, wherein each queue can accommodate a plurality of entries of commands from one of the VMs 110. As discussed above, the commands in the submission queue 212 are first fetched by the NQM 204 from the memory 210 of the host 106 to the waiting buffer 218 of the NVMe processing engine 202 as discussed above. During its operation, each of the virtual NVMe controllers 104 retrieves the commands of its corresponding VM 110 from the waiting buffer 218 and processes the commands on the data to be written or read accordingly to the logic volume via the NVMe processing engine 202, by invoking supporting VF functions provided by the physical NVMe controller 102. [0025]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the controller/hardware accelerator of Hussain with the namespace management features of Yang and Yoshida resulting in the controller creating the application specific namespaces and allocating corresponding hardware queues from the hardware accelerator to those namespaces. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].
With regards to claim 7, Yang and Hussain teach the namespace management system of claim 1 using application-specific namespaces and corresponding hardware queues.Hussain further teaches wherein the host has a virtual machine running thereon, and the multiple applications run in the virtual machine, the virtual machine comprises a driver ( each of the VMs 110 running on the host 106 has an NVMe driver 114 configured to interact with the physical NVMe controller 102 and the virtual NVMe controllers 104 via the PCIe/NVMe link/connection 111. [0026])configured to manage the multiple hardware queues (When transmitting commands and/or data to and/or from a VM 110, the corresponding VF NVMe driver 114 directly puts and/or retrieves the commands and/or data from its queues and/or the data buffer, which is sent out or received from the PCIe/NVMe link/connection 111 without the data being accessed by the host 106 or any other VMs 110 running on the same host 106. [0027])Yang and Hussain do not teach that the namespace creating request itself is sent via the driver.However, in analogous art, Yoshida teaches wherein the sending, by the host, the namespace creation request to the offloading card, comprises: sending, by the virtual machine, the namespace creation request to the offloading card via the driver. (The application program 201A (or 201B) calls the library 401 using a function call for requesting the creation of the I/O submission queue, thereby requesting the library 401 to transmit an I/O submission queue creation request to the kernel 302 [0126]. the driver 304 of the kernel 302 executes an operation of storing the I/O submission queue creation request in the admin submission queue 601 and an operation of notifying the SSD 3 that a new management request…is stored in the admin submission queue 601 [0129]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the submission queue creation request transmitted through the driver of Yoshida with the VM/driver architecture of Hussain and the offloading card architecture of Yang resulting in the VM sending the submission queue creation request to the offloading card via the driver. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of ensuring that even when a delay in I/O processing with respect to one namespace occurs, a delay in I/O processing with respect to the other namespace can be prevented in at least Yoshida [0147].
With regards to claim 8, Yang, Hussain, and Yoshida teach the namespace-management system of claim 7 using VM-based applications, a driver, and namespace specific hardware queues. Hussain further teaches wherein the offloading card comprises a controller and a hardware accelerator (Each VF shares one or more physical resources on the physical NVMe controller 102, wherein such resources include but are not limited to on-controller memory, hardware accelerator and storage interface 118 of the physical NVMe controller 102. [0017]. The hardware implementation includes at least an NVMe processing engine 202, and an NVMe Queue Manager (NQM) 204 implemented to support the NVMe processing engine 202. the NQM 204 manages at least a submission queue 212...and a completion queue 214 [0018]).wherein the creating, by the offloading card, the corresponding multiple namespaces for the multiple applications, according to the namespace creation request, comprises: creating, by the controller, respective namespaces for the multiple applications according to the namespace creation request (a plurality of virtual NVMe controllers are created on a single physical NVMe controller...and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller. [0011])wherein the allocating, by the offloading card, the multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binding the allocated multiple hardware queues respectively to the corresponding namespaces, comprises: allocating, by the controller, the multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binding the allocated multiple hardware queues respectively to the corresponding namespaces. (each of the virtual NVMe controllers 104 has one or more pairs of submission queue 212 and completion queue 214 associated with it, wherein each queue can accommodate a plurality of entries of commands from one of the VMs 110. As discussed above, the commands in the submission queue 212 are first fetched by the NQM 204 from the memory 210 of the host 106 to the waiting buffer 218 of the NVMe processing engine 202 as discussed above. During its operation, each of the virtual NVMe controllers 104 retrieves the commands of its corresponding VM 110 from the waiting buffer 218 and processes the commands on the data to be written or read accordingly to the logic volume via the NVMe processing engine 202, by invoking supporting VF functions provided by the physical NVMe controller 102. [0025]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the controller/hardware accelerator of Hussain with the namespace management features of Yang and Yoshida resulting in the controller creating the application specific namespaces and allocating corresponding hardware queues from the hardware accelerator to those namespaces. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].
Claims 4, 5, 9, 10, 12, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang Pub. No. CN 111198663 A (hereafter Yang), citations correspond to English translation provided herewith, in view of Hussain et al. Pub. No. US 2015/0317088 A1 (hereafter Hussain) and in further view of Yoshida Pub. No. US 2021/0042246 A1 (hereafter Yoshida) as applied to claims 1, 2, 3, 6, 7, 8, 13, and 14 above, and in further view of Hu et al. Pub. No. CN 110309001A (hereafter Hu), citations correspond to English translation provided herewith.
With regards to claim 4, Yang, Hussain, and Yoshida teach the namespace management system of claim 3 using VM-based applications, dedicated namespaces, and corresponding hardware queues. Yoshida further teaches wherein the virtual machine comprises a user space and a kernel space...and the driver (A memory space (or virtual memory space) managed by the processor 41 includes a user space 101 and a kernel space 102. The user level software operates in the user space 101, and the in-kernel software operates in the kernel space 102 [0044] The OS 301 includes a kernel 302. The kernel 302 includes a file system 303, a driver 304, and the like. The driver 304 is a device driver for controlling the SSD 3. [0047])Yoshida does not teach the multicore CPU, applications being executed by corresponding CPU cores or the general block layer.However, in analogous art, Hu teaches wherein the host comprises a central processing unit with multiple cores, the user space has the multiple applications running therein, the applications are executed by corresponding cores (As shown in Figure 2, the software queue is associated with the central processing unit core. Generally, one processor core is associated with one software queue. The software queue is mainly used to cache the data sent by the processor core. [0055] the bio sent by the upper-layer application will be stored in the software queue associated with the CPU core that executes its application thread.[0066])and wherein the kernel space comprises a general block layer and the driver, the general block layer comprises multiple software queues corresponding to the multiple cores (Generic Block Layer: The generic block layer is a kernel component [0047] Typically, the mapping relationship between software queues and central processing units is one-to-one, meaning that a software queue is associated with only one processor core. [0055])and establishes a one-to-one corresponding relationship from the multiple software queues to the multiple hardware queues. (in the existing Linux general block layer multi-queue framework before optimization, each software queue can only send requests through a single hardware queue...this embodiment provides an optimization system based on Linux general block layer multi-queue, which improves the mapping relationship between software queues and hardware queues from many-to-one or one-to-one to many-to-many, that is, a software queue will establish a mapping relationship with each hardware queue [0050]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the multicore general block layer and software hardware queues of Hu with the features of Yang, Hussain, and Yoshida resulting in applications executing on corresponding CPU cores and a kernel-space general block layer having per-core software/hardware queues. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of realizing parallel operation of I/O requests...improving the processing efficiency of I/O requests and increasing I/O throughput in at least Hu [0010].
With regards to claim 5, Yang, Hussain, Yoshida, and Hu teach the system of claim 4, using the VM based namespace architecture and corresponding software and hardware queues. Yang further teaches wherein the host is connected to an NVMe device via the offloading card (The storage offloading card 200 connects to an NVMe-compliant solid-state drive via a PCIe (Peripheral Component Interconnect express) bus, and the storage offloading card connects to the server via a PCIe bus. [0058])wherein the offloading card sends the input/output request conforming with the NVMe protocol to the NVMe device. (the server can send instructions to the storage offload card to execute the virtual functions loaded by the multiple virtual machines installed in the operating system. When the storage offload card receives the instructions, it can create namespaces corresponding to each virtual function in the solid-state drive for the implementation of the virtual functions and perform data access operations in the namespaces. The data access operations performed in each namespace are related to the virtual function corresponding to that namespace. [0060])Hussain further teaches wherein the driver is Non-Volatile Memory Host Controller Interface Specification (NVMe) driver, the controller is an NVMe controller (each of the VMs 110 running on the host 106 has an NVMe driver 114 configured to interact with the physical NVMe controller 102 and the virtual NVMe controllers 104 via the PCIe/NVMe link/connection 111 [0026]) wherein the NVMe device is mounted inside the virtual machine (Each virtual NVMe controller 104 is assigned to and dedicated to support one and only one of the VMs 110 to access its storage devices [0021])and the input/output request conforming with the NVMe protocol is sent to the NVMe controller (each of the NVMe driver 114...configured...to set up a communication path between its corresponding VM 110 and a virtual NVMe controller 104 and to receive and transmit data associated with the corresponding VM 110. [0026])wherein the NVMe controller transfers the input/output request conforming with the NVMe protocol to the offloading card via the hardware queues corresponding to the created namespaces (each of the virtual NVMe controllers 104 has one or more pairs of submission queue 212 and completion queue 214 associated with it, wherein each queue can accommodate a plurality of entries of commands from one of the VMs 110 [0025])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the NVMe driver and controller features of Hussain with the features of Yang and the combination of claim 4 resulting in the virtual manchine using an NVMe driver to transmit NVMe-protocol I/O request to the NVMe controller. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].Hu further teaches wherein an application running in the user space issues an input/output request to the general block layer (bio represents a request from the general block layer, indicating a request from the upper-layer application software. When upper-layer applications need to write data to the disk or read data from the disk, the requests will eventually be converted into bio requests at the general block layer. [0048])wherein the input/output request is converted into an input/output request conforming with an NVMe protocol by processing of the general block layer and the NVMe driver (When a bio request from the general block layer is submitted to the block device driver, a corresponding block device driver layer request needs to be constructed and inserted into the block device request queue. [0049])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the general block layer I/O processing features of Hu with the NVMe driver/controller and namespace specific queue features of Yang and Hussain and the combination of claim 4, resulting in the application I/O request being processed through the general block layer and NVMe driver before being transmitted through the namespace associated hardware queue. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of realizing parallel operation of I/O requests...improving the processing efficiency of I/O requests and increasing I/O throughput in at least Hu [0010].
With regards to claim 9, Yang, Hussain, and Yoshida teach the namespace management method of claim 8 using VM-based applications, dedicated namespaces, and corresponding hardware queues. Yoshida further teaches wherein the virtual machine comprises a user space and a kernel space...and the driver (A memory space (or virtual memory space) managed by the processor 41 includes a user space 101 and a kernel space 102. The user level software operates in the user space 101, and the in-kernel software operates in the kernel space 102 [0044] The OS 301 includes a kernel 302. The kernel 302 includes a file system 303, a driver 304, and the like. The driver 304 is a device driver for controlling the SSD 3. [0047])Yoshida does not teach the multicore CPU, applications being executed by corresponding CPU cores or the general block layer.However, in analogous art, Hu teaches wherein the host comprises a central processing unit with multiple cores, the user space has the multiple applications running therein, the applications are executed by corresponding cores (As shown in Figure 2, the software queue is associated with the central processing unit core. Generally, one processor core is associated with one software queue. The software queue is mainly used to cache the data sent by the processor core. [0055] the bio sent by the upper-layer application will be stored in the software queue associated with the CPU core that executes its application thread.[0066])and wherein the kernel space comprises a general block layer and the driver, the general block layer comprises multiple software queues corresponding to the multiple cores (Generic Block Layer: The generic block layer is a kernel component [0047] Typically, the mapping relationship between software queues and central processing units is one-to-one, meaning that a software queue is associated with only one processor core. [0055])and establishes a one-to-one corresponding relationship from the multiple software queues to the multiple hardware queues. (in the existing Linux general block layer multi-queue framework before optimization, each software queue can only send requests through a single hardware queue...this embodiment provides an optimization system based on Linux general block layer multi-queue, which improves the mapping relationship between software queues and hardware queues from many-to-one or one-to-one to many-to-many, that is, a software queue will establish a mapping relationship with each hardware queue [0050]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the multicore general block layer and software hardware queues of Hu with the features of Yang, Hussain and Yoshida resulting in applications executing on corresponding CPU cores and a kernel-space general block layer having per-core software/hardware queues. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of realizing parallel operation of I/O requests...improving the processing efficiency of I/O requests and increasing I/O throughput in at least Hu [0010].
With regards to claim 10, Yang, Hussain, Yoshida, and Hu teach the method of claim 9, using the VM based namespace architecture and corresponding software and hardware queues.Yang further teaches wherein the host is connected to an NVMe device via the offloading card, wherein the method further comprises (The storage offloading card 200 connects to an NVMe-compliant solid-state drive via a PCIe (Peripheral Component Interconnect express) bus, and the storage offloading card connects to the server via a PCIe bus. [0058].)wherein the offloading card sends the input/output request conforming with the NVMe protocol to the NVMe device. (the server can send instructions to the storage offload card to execute the virtual functions loaded by the multiple virtual machines installed in the operating system. When the storage offload card receives the instructions, it can create namespaces corresponding to each virtual function in the solid-state drive for the implementation of the virtual functions and perform data access operations in the namespaces. The data access operations performed in each namespace are related to the virtual function corresponding to that namespace. [0060])Hussain further teaches wherein the driver is Non-Volatile Memory Host Controller Interface Specification (NVMe) driver, the controller is an NVMe controller (each of the VMs 110 running on the host 106 has an NVMe driver 114 configured to interact with the physical NVMe controller 102 and the virtual NVMe controllers 104 via the PCIe/NVMe link/connection 111 [0026]) wherein the NVMe device is mounted inside the virtual machine (Each virtual NVMe controller 104 is assigned to and dedicated to support one and only one of the VMs 110 to access its storage devices [0021])and the input/output request conforming with the NVMe protocol is sent to the NVMe controller (each of the NVMe driver 114...configured...to set up a communication path between its corresponding VM 110 and a virtual NVMe controller 104 and to receive and transmit data associated with the corresponding VM 110. [0026])wherein the NVMe controller transfers the input/output request conforming with the NVMe protocol to the offloading card via the hardware queues corresponding to the created namespaces (each of the virtual NVMe controllers 104 has one or more pairs of submission queue 212 and completion queue 214 associated with it, wherein each queue can accommodate a plurality of entries of commands from one of the VMs 110 [0025])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the NVMe driver and controller features of Hussain with the features of Yang and the combination of claim 4 resulting in the virtual manchine using an NVMe driver to transmit NVMe-protocol I/O request to the NVMe controller. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].Hu further teaches wherein an application running in the user space issues an input/output request to the general block layer (bio represents a request from the general block layer, indicating a request from the upper-layer application software. When upper-layer applications need to write data to the disk or read data from the disk, the requests will eventually be converted into bio requests at the general block layer. [0048])wherein the input/output request is converted into an input/output request conforming with an NVMe protocol by processing of the general block layer and the NVMe driver (When a bio request from the general block layer is submitted to the block device driver, a corresponding block device driver layer request needs to be constructed and inserted into the block device request queue. [0049])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the general block layer I/O processing features of Hu with the NVMe driver/controller and namespace specific queue features of Yang and Hussain and the combination of claim 4, resulting in the application I/O request being processed through the general block layer and NVMe driver before being transmitted through the namespace associated hardware queue. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of realizing parallel operation of I/O requests...improving the processing efficiency of I/O requests and increasing I/O throughput in at least Hu [0010].
With regards to claim 12, Yang teaches a method for processing an input/output request, wherein the method runs in a system for processing an input/output request, the system for processing the input/output request comprises a host, an offloading card, and ana Non-Volatile Memory Host Controller Interface Specification (NVMe) device connected to the host via the offloading card (The system includes a server 100, a storage offloading card 200, and a solid-state drive 300. [0056] Virtual machine 110 is installed in the operating system of server 100. The storage offloading card 200 connects to an NVMe-compliant solid-state drive via a PCIe (Peripheral Component Interconnect express) bus, and the storage offloading card connects to the server via a PCIe bus.[0058]).and sending, by the offloading card, the input/output request conforming with the NVMe protocol to the NVMe device.(the server can send instructions to the storage offload card to execute the virtual functions loaded by the multiple virtual machines installed in the operating system. When the storage offload card receives the instructions, it can create namespaces corresponding to each virtual function in the solid-state drive for the implementation of the virtual functions and perform data access operations in the namespaces. The data access operations performed in each namespace are related to the virtual function corresponding to that namespace. [0060])Hussain further teaches wherein the host has a virtual machine running thereon (each of the VMs 110 running on the host 106 has an NVMe driver 114 configured to interact with the physical NVMe controller 102 and the virtual NVMe controllers 104 via the PCIe/NVMe link/connection 111. [0026])wherein the NVMe driver is configured to manage the multiple hardware queues (When transmitting commands and/or data to and/or from a VM 110, the corresponding VF NVMe driver 114 directly puts and/or retrieves the commands and/or data from its queues and/or the data buffer, which is sent out or received from the PCIe/NVMe link/connection 111 without the data being accessed by the host 106 or any other VMs 110 running on the same host 106. [0027]) wherein the offloading card comprises an NVMe controller and a hardware accelerator (Each VF shares one or more physical resources on the physical NVMe controller 102, wherein such resources include but are not limited to on-controller memory, hardware accelerator and storage interface 118 of the physical NVMe controller 102. [0017]. The hardware implementation includes at least an NVMe processing engine 202, and an NVMe Queue Manager (NQM) 204 implemented to support the NVMe processing engine 202. the NQM 204 manages at least a submission queue 212...and a completion queue 214 [0018]).the NVMe controller creates respective namespaces for the multiple applications according to the namespace creation request (a plurality of virtual NVMe controllers are created on a single physical NVMe controller...and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller. [0011])allocates multiple hardware queues corresponding to the created multiple namespaces from the hardware accelerator and binds the allocated multiple hardware queues respectively to the corresponding namespaces (the hardware resource management scheme in the HW is manifested as the management port of the NVMe SSD, which is responsible for the initialization, resource configuration and allocation of queues and namespaces of the NVMe SSD...after the PF/VF is uniformly bound with the namespace and queue resources through a specific binding mechanism [0143]).and the input/output request conforming with the NVMe protocol is sent to the NVMe controller (each of the NVMe driver 114...configured...to set up a communication path between its corresponding VM 110 and a virtual NVMe controller 104 and to receive and transmit data associated with the corresponding VM 110. [0026])transferring, by the NVMe controller, the input/output request conforming with the NVMe protocol to the offloading card via the hardware queues corresponding to the created namespaces (each of the virtual NVMe controllers 104 has one or more pairs of submission queue 212 and completion queue 214 associated with it, wherein each queue can accommodate a plurality of entries of commands from one of the VMs 110 [0025])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the VM-specific NVMe namespace and hardware queue features of Hussain with the namespace creation features of Yang resulting in each namespace having dedicated queue resources through with I/O for that namespace can be independently processed.A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of enabling VMs to each have dedicated access to its own storage namespace which improves latency, performance, data security and integrity for the VMs in at least Hussain [0012].Yoshida teaches the virtual machine sends a namespace creation request to the offloading card via the NVMe driver (The application program 201A (or 201B) calls the library 401 using a function call for requesting the creation of the I/O submission queue, thereby requesting the library 401 to transmit an I/O submission queue creation request to the kernel 302 [0126]. the driver 304 of the kernel 302 executes an operation of storing the I/O submission queue creation request in the admin submission queue 601 and an operation of notifying the SSD 3 that a new management request…is stored in the admin submission queue 601 [0129]).It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the submission queue creation request transmitted through the driver of Yoshida with the VM/driver and the offloading card architecture of Yang resulting in the VM sending the submission queue creation request to the offloading card via the driver. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of ensuring that even when a delay in I/O processing with respect to one namespace occurs, a delay in I/O processing with respect to the other namespace can be prevented in at least Yoshida [0147].wherein the virtual machine comprises the kernel space comprises and an NVMe driver (A memory space (or virtual memory space) managed by the processor 41 includes a user space 101 and a kernel space 102. The user level software operates in the user space 101, and the in-kernel software operates in the kernel space 102 [0044] The OS 301 includes a kernel 302. The kernel 302 includes a file system 303, a driver 304, and the like. The driver 304 is a device driver for controlling the SSD 3. [0047])Yang, Hussain, and Yoshida do not teach the multi core general block layer software queue mapping.However, in analogous art, Hu teaches the host comprises a central processing unit with multiple cores, the user space has the multiple applications running therein, the applications are executed by corresponding cores (As shown in Figure 2, the software queue is associated with the central processing unit core. Generally, one processor core is associated with one software queue. The software queue is mainly used to cache the data sent by the processor core. [0055] the bio sent by the upper-layer application will be stored in the software queue associated with the CPU core that executes its application thread.[0066])a general block layer and, the general block layer comprises multiple software queues corresponding to the multiple cores (Generic Block Layer: The generic block layer is a kernel component [0047] Typically, the mapping relationship between software queues and central processing units is one-to-one, meaning that a software queue is associated with only one processor core. [0055])the general block layer establishes a one-to-one correspondence relationship from the multiple software queues to the multiple hardware queues, wherein the method further comprises: (in the existing Linux general block layer multi-queue framework before optimization, each software queue can only send requests through a single hardware queue...this embodiment provides an optimization system based on Linux general block layer multi-queue, which improves the mapping relationship between software queues and hardware queues from many-to-one or one-to-one to many-to-many, that is, a software queue will establish a mapping relationship with each hardware queue [0050]).issuing, by an application running in the user space, an input/output request to the general block layer; (bio represents a request from the general block layer, indicating a request from the upper-layer application software. When upper-layer applications need to write data to the disk or read data from the disk, the requests will eventually be converted into bio requests at the general block layer. [0048])converting, by processing of the general block layer and the NVMe driver, the input/output request into an input/output request conforming with NVMe protocol (When a bio request from the general block layer is submitted to the block device driver, a corresponding block device driver layer request needs to be constructed and inserted into the block device request queue. [0049])It would have been obvious to a person have ordinary skill in the art prior to the effective filing date of the claimed invention to combine the general block layer I/O processing features of Hu with the NVMe driver/controller and namespace specific queue features of Yang and Hussain and the combination of claim 9, resulting in the application I/O request being processed through the general block layer and NVMe driver before being transmitted through the namespace associated hardware queue. A person having ordinary skill in the art would have motivated to make this combination, with a reasonable expectation of success for the purpose of realizing parallel operation of I/O requests...improving the processing efficiency of I/O requests and increasing I/O throughput in at least Hu [0010].With regards to claim 15, Yang, Hussain, Yoshida, and Hu teach the method of claim 12.Yang further teaches an electronic device, comprising a memory and a processor; wherein the memory is configured to store one or more pieces of computer instructions, the one or more pieces of computer instructions are executed by the processor to implement steps of the method according to claim 12 (embodiments of the present invention provide an apparatus for controlling data access operations, the apparatus including a memory and a processor; Memory is used to store computer-readable instructions; The processor is used to read computer-readable instructions to perform the following operations [0030]-[0032])With regards to claim 16, Yang, Hussain, Yoshida, and Hu teach the method of claim 12.Yang further teaches a non-transitory readable storage medium, storing computer instructions, wherein when the computer instructions are executed by a processor, steps of the method according to claim 12 are implemented (a storage medium comprising a stored program, wherein the program is executed by a processor to perform the method described in any of the above embodiments. [0097])
Conclusion
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/T.J.J./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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