DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities:
Claim 5, Line 6, “registerHRCAP2” is expected to read “register HRCAP2”.
Claim 5, Line 8, “registerHRCAP3” is expected to read “register HRCAP3”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "a periodic sampling clock signal HRCLK" in lines 4-5. A periodic sampling clock signal HRCLK has been previously introduced in claim 1, of which claim 2 depends upon. It is unclear if the claim is referring to the aforementioned HRCLK signal or introducing an additional periodic sampling clock signal. Further clarification is necessary. For examination purposes, examiner has interpreted “a periodic sampling clock signal HRCLK” to read “the periodic sampling clock signal HRCLK”.
By virtue of its dependency on claim 2, claim 3 is also rejected.
Allowable Subject Matter
Claims 2-3 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 1, 4, & 6 are allowed.
Regarding claim 1, Chen et al. (US 11,852,666 B2), hereinafter Chen, discloses, in figure 2, a high-precision pulse width measurement circuit, comprising:
a sampling clock and calibration clock circuit (top portion), comprising a group of delay units (delay units DLL), wherein each of the delay units is used for outputting a periodic sampling clock signal HRCLK (col. 5, lines 44-48, sampling output level of each time delay unit DLL when the next HRCAPCLK clock rising edge is coming);
a sampling circuit (integer encoding unit), only working in a clock domain of the sampling clock signal HRCLK and comprising a counter HRCNT (Counter [n:1]), four capture registers HRCAP1-HRCAP4 (registers CNTR1, CNTR2, CNTF1, CNTF2), an edge detection circuit (edge detection and interrupt control unit), and an interrupt control circuit (edge detection and interrupt control unit); and
a calibration circuit (calibration control and decimal encoding unit), comprising bit capture registers CALCAP and SYSCAP (col. 6, lines 59-61, “calibration registers CALR1[m:1] and CALR2 [m:1] are controlled by a calibration controller”), a bit register CALPRD (step size register STEP [m:1])
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
the clock frequency divider is used for generating, according to the sampling clock signal HRCLK, a low-frequency clock signal CALCLK for sampling precision calibration, and wherein after setting a calibration enable signal CALEN=1, the counters CALCNT and SYSCNT start to count from 0; when a value of the counter SYSCNT is equal to a value of the bit register CALPRD the comparator generates a high-level pulse CALDONE indicating the completion of one calibration period, and values of the counters CALCNT and SYSCNT are triggered to be loaded into the bit capture registers CALCAP and SYSCAP, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tessarolo et al. (US 8,384,440 B2) [Figure 5. Discloses high resolution capture (HRCAP) of this invention which enables time stamping of input signals with very high resolution without requiring high frequency sampling. This invention uses a capture delay line to time stamp an input edge signal as a fraction of the input signal sampling frequency. The capture delay line includes a first input receiving a synchronized signal and a second input receiving the input signal. These inputs propagate toward one another within a sequence of bit circuits. The meeting location within the sequence of bit circuits indicates a time of the input signal transition at a resolution greater than possible via the sampling frequency clock.]
Zerbe et al. (US 2014/0035650 A1) [Figure 10A. Discloses a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.]
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/TYLER J PERENY/ Examiner, Art Unit 2836
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