Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/05/2026 have been fully considered but they are not persuasive.
Regarding 112(b) rejections in claims 1, 7 and 13, applicant argued that “zT values” are not indefinite because it is well-known in the art and defined in filed specification.
However, examiner respectfully disagrees. Although the thermoelectric figure of merit is the most prevalent, without additional context, such as explicit mentions of thermal conductivity or the Seebeck coefficient, with only "of semiconductor components of the wafer" showing association of “zT values” can be interpreted in alternative ways. For example, zT values could be interpreted as measurement or output data from a “2830 ZT Wafer Analyzer” designed specifically for semiconductor industry. So, outside of terminology in material physics, “zT values” can be interpreted alternatively in association with machine labeling output data “of semiconductor components of the wafer.” Despite of applicant’s argument, the phrase "zT values" would require additional context to correlate applicant’s intended definition.
Thus, rejections are proper and maintained.
Regarding 103 rejections on claims 1, 7 and 13, applicant argued that prior arts fail to teach the specification defined “zT values” because Majundar is explicitly directed to metrology for standard CMOS and memory cells. Applicant then argued there is no reason to combine the prior arts because neither reference mentions zT values or thermoelectric properties as defined in filed specification. Applicant further argued the combination would force Majumdar’s system to rely on electron microscopy (SEM) requiring vacuum chambers, which would defeat Majumdar’s core objective of rapid, inline optical metrology.
However, examiner respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., dimensionless figure of merit) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As explained in response to 112(b) rejection above, “zT values” could be interpreted as output data from a wafer analyzer (an advanced thin-film metrology tool) which is “of semiconductor components of the wafer”. Also, the argued claim does not exclude metrology for standard CMOS and memory cells.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). Despite of applicant’s conclusion, applicant’s argument is based on the interpretation that “zT values” must be the dimensionless figure of merit disclosed in filed specification. But the argued term is interpreted differently in argued 103 rejection as explained above. So, applicant’s argument is moot.
While Akers do not disclose vacuum chamber, it is well-known in the art that scanning electron microscopy (SEM) can be performed without a traditional specimen vacuum chamber. So, unlike applicant’s assumption, combination would not defeat the intended purpose of Majumdar. Moreover, intended purpose of Majumdar is relative, but not absolute to application with SEM.
Thus, rejections are proper and maintained.
Regarding rejections on claims 3, 9 and 15, applicant argued that Thiry is non-analogous art because it is for use in spacecraft.
However, examiner respectively disagrees. Despite of applicant’s argument, Thiry is an analogous art in computer vision, such as using deep learning algorithm to achieve computer vision tasks, such as image classification, object detection, etc.
Thus, rejections are proper and maintained.
Regarding rejections on claims 6, 12 and 18, applicant argued that using Lal’s bismuth tellurium teaching in combination would be highlight reconstruction.
However, examiner respectfully disagrees. When configuring semiconductor wafer from bismuth tellurium is known in prior arts, claiming such feature would not be an inventive concept. Moreover, despite applicant’s argument, bismuth tellurium is a predictable choice from a limited set of options that a skilled person would naturally test with a reasonable chance of success. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Thus, rejections are proper and maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In independent claims 1, 7 and 13, “zT values” is indefinite without further clarification in claim limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7-8, 10-11, 13-14, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumdar et al. (US2020/0051235) in view of Akers et al. (US2023/0419695).
To claim 1, Majumdar teach a system (Figs. 1-2), comprising:
a database comprising a plurality of training datasets, each training dataset comprising a scanning electron microscope (SEM) image of a semiconductor wafer (image data sets) and zT values (measured metrology data) of semiconductor components of the wafer (paragraph 0034, electrical performance metrics; paragraphs 0047, 0060, performance index analyses, or figure of merit); and
a processor operable to implement a machine learning module that, when trained with the training datasets, is operable to process an input dataset of another semiconductor wafer through the machine learning module to predict zT values of semiconductor components of the other wafer, the input dataset of the other wafer comprising an SEM image of the other wafer (paragraphs 0046, 0050, predictive models are trained to from analysis on other wafers)
But, Majumdar do not expressly disclose an energy-dispersive spectroscopy (EDS/EDAX) image of the wafer, an electron backscatter diffraction (EBSD) image of the wafer
However, EDS/EDAX image and EBSD image are well-known techniques of SEM imaging.
Akers teach using artificial intelligence assisted analysis of electron microscope data (abstract, paragraphs 0033, 0049), wherein training dataset comprising a scanning electron microscope (SEM) image (paragraphs 0010), an energy-dispersive spectroscopy (EDS/EDAX) image (paragraph 0059), an electron backscatter diffraction (EBSD) image (paragraph 006).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Akers into the system of Majumdar, in order to implement image training data sets by design preference.
To claim 7, Majumdar and Akers teach a computer implemented method (as explained in response to claim 1 above).
To claim 13, Majumdar and Akers teach a non-transitory computer readable medium comprising instructions that, when executed by a processor, direct the processor to execute (as explained in response to claim 1 above).
To claims 2, 8 and 14, Majumdar and Akers teach claims 1, 7 and 13.
Majumdar and Akers teach wherein: the machine learning module is operable to identify grain boundaries of the other wafer (Akers, paragraphs 0005, 0031, grain boundaries).
To claims 4, 10 and 16, Majumdar and Akers teach claims 1, 7 and 13.
Majumdar and Akers teach wherein: the machine learning module is operable to identify crystalline properties of the other wafer (Akers, paragraphs 0032-0033, 0062-0063, crystal structures).
To claims 5, 11 and 17, Majumdar and Akers teach claims 1, 7 and 13.
Majumdar and Akers teach wherein: the machine learning module comprises at least one of a supervised learning algorithm, a semi-supervised learning algorithm, an unsupervised learning algorithm, a regression analysis algorithm, a reinforcement learning algorithm, a self-learning algorithm, a feature learning algorithm, a sparse dictionary learning algorithm, an anomaly detection algorithm, a generative adversarial network, a convolutional neural network, a transfer learning algorithm, or an association rules algorithm (Majumdar, paragraph 0049).
Claim(s) 3, 9, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumdar et al. (US2020/0051235) in view of Akers et al. (US2023/0419695) and Thiry (US2024/0029833).
To claims 3, 9 and 15, Majumdar and Akers teach claims 2, 8 and 14.
Despite of obviousness to one of ordinary skill in the art, Majumdar and Akers do not expressly disclose wherein: the machine learning module is operable to identify precipitates at the grain boundaries of the other wafer.
Thiry teach the machine learning module is operable to identify precipitates at the grain boundaries of the other wafer (paragraphs 0056, 0071, 0132), which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate into the system, method and apparatus of Majumdar and Akers, in order to further machine learning module identification.
Claim(s) 6, 12, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majumdar et al. (US2020/0051235) in view of Akers et al. (US2023/0419695) and Lal et al. (US2012/0322164).
To claims 6, 12 and 18, Majumdar and Akers teach claims 1, 7 and 13.
But, Majumdar and Akers do not expressly disclose wherein: the semiconductor wafer is configured from bismuth tellurium.
Lal teach the semiconductor wafer configured from bismuth tellurium (paragraph 0087), which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate into the system, method and apparatus of Majumdar and Akers, in order to further semiconductor wafer by design preference.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIYU LU whose telephone number is (571)272-2837. The examiner can normally be reached Weekdays: 8:30AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephen R Koziol can be reached at (408) 918-7630. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ZHIYU . LU
Primary Examiner
Art Unit 2669
/ZHIYU LU/Primary Examiner, Art Unit 2665 September 28, 2026
