Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, filed on 03/12/2026, are acknowledged. Amended claims 1-12 are acknowledged. Accordingly, claims 1-12 are pending and have been examined.
Response to Arguments
3. Applicant's arguments have been fully considered but they are not persuasive.
The Applicant argues/remarks, on pg. 8 of 11, that Ikuma fails to teach the features to
“sequentially amplify the pixel signal with a gain of the plurality of gains; and
generate, from an exposure operation, a plurality of pieces of image data based on the sequential amplification of the pixel signal”.
However, Ikuma, in [0195], teaches gain detection circuit 401 (or 402) for a pixel signal from the sample and hold circuit (Fig. 6A or 7); as such high, middle, and low conversion gains; wherein these are sequentially processed in accordance with the function of the apparatus and exposure functions. Wherein after the readout is performed, the signal is further processed and eventually a digital pixel signal is held in memory, in accordance with the schematic layout of Fig. 1.
Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-2, 5, 7-9, and 12 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated
by Ikuma et al. (US 2024/0121533 A1; further referred to as Ikuma).
6. Regarding claim 1, a solid-state imaging element (…Ikuma, in [0135], teaches a solid state imaging apparatus; Fig. 3…), comprising:
a pre-stage circuit configured to generate a pixel signal (…[0135] teaches a pixel circuit 3a; Fig. 3…);
a sample-and-hold circuit (…(…[0135] teaches sample and hold circuit SH10 connected to circuit 3a; Fig. 3…) configured to:
hold the pixel signal over a holding period (…wherein [0152] teaches that SH10 holds a plurality of pixel signals before a particular readout is performed…); and
output the pixel signal a plurality of times within the holding period (…wherein [0152] further teaches that the plurality of pixel signals are supplied to a subsequent circuit after being sampled and held…);
a timing control circuit (…wherein [0120] teach a timing controller 20 which generates control signals of the imaging apparatus 100; Fig. 1…) configured to
sequentially designate, within the holding period, a plurality of gains with a control signal (…[0195] teaches gain detection circuit 401 (or 402) for a pixel signal from the sample and hold circuit (Fig. 6A or 7); as such high, middle, and low conversion gains; wherein these are sequentially processed in accordance with the function of the apparatus and exposure functions…); and
an amplifier circuit configured to sequentially amplify the pixel signal with a gain of the plurality of gains (…wherein Ikuma, in [0112], teaches an amplification transistor SF1 which may be viewed as an amplification circuit along with corresponding amplification value that delivers a pixel signal with a particular amplification value; Ikuma also teaches SF2 and SEL_GS, as taught in [0176] and depicted in Fig. 3, being connected to vertical signal line 30A; and further in [0195], Ikuma teaches a first detection circuit 401 which detects what gain a pixel signal is correspondent to and transmits these as signal selection signals 407 to selection circuit 400. Further, signals 407 are provided to a voltage comparator 252 as gain selection signals, through vertical signal line 19B and amplification transistor SF30 (see [0196] and Fig. 12). Thus, voltage comparator 252 can be viewed as an amplifier circuit…); and
generate, from an exposure operation, a plurality of pieces of image data based on the sequential amplification of the pixel signal (…wherein after the readout is performed, the signal is further processed and eventually a digital pixel signal is held in memory, in accordance with the schematic layout of Fig. 1…).
7. Regarding claim 2, Ikuma teaches the solid-state imaging element according to claim 1
(see claim 1 above), wherein
the amplifier circuit includes a comparator that is configured to compare the pixel signal with a ramp signal (…[0233] teaches that the voltage comparator 252 compares
gains selection signals with ramp signal; wherein [0127] teaches that a reference ramp
signal generator 22 generates reference signal ramp and provides the same to
comparator 252…).
8. Regarding claim 5, Ikuma teaches the solid-state imaging element according to claim 1
(see claim 1 above), further comprising
an analog-to-digital converter configured to perform an analog-to-digital conversion process on the pixel signal (…wherein [0119] teaches ADC input lines ADIN1-ADINm; Fig. 1…), wherein
the amplifier circuit includes a column amplifier that is configured to supply the amplified pixel signal to the analog-to-digital converter (…wherein [0123] teaches that each column AD circuit comprises a comparator (amplifier), counter and memory; Fig. 1 depicts these elements as emboxed element “ADIN”; as such the comparator supplies a signal comparison output for digital conversion…).
9. Regarding claim 7, Ikuma teaches the solid-state imaging element according to claim 1
(see claim 1 above), further comprising
an analog-to-digital converter configured to perform an analog-to-digital conversion process on the pixel signal (…wherein [0119] teaches ADC input lines ADIN1-ADINm; Fig. 1; [0123] teaches that each column AD circuit comprises a comparator, counter and memory; Fig. 1 depicts these elements as emboxed element “ADIN”…), wherein
the amplifier circuit is further configured to amplify the pixel signal based on the analog-to-digital conversion process (…wherein [0123] teaches that each column AD circuit comprises a comparator, counter and memory; Fig. 1 depicts these elements as emboxed element “ADIN”; as such the comparator (amplifier) supplies a signal comparison output for digital conversion…).
10. Regarding claim 8, Ikuma teaches the solid-state imaging element according to claim 1
(see claim 1 above), further comprising
a post-stage reset transistor (…wherein, as taught in [0316] with regards to Fig. 15,
at various times (e.g. t116 and t118), charge accumulated as parasitic capacitance at the
gate of SF30 (Fig. 7) may be discharged by the operation of switch element SW21; thus
SW21 may be viewed as a reset transistor…), wherein
the sample-and-hold circuit includes:
a first capacitor element and a second capacitor element (…wherein the sample and hold circuit of Fig. 7 depicts numerous capacitors (C30-C35)…); and
a selection circuit (…wherein Fig. 7 depicts a parallel connection between
capacitors C30-C35 from which a selection of transmission is possible…) that is configured to
sequentially perform control to connect one of the first capacitor element or second
the second capacitor element to a post-stage node (…wherein [0335-0338] teach signal
readout from the sample and hold circuit by activating an amplification transistor SF2
and thereafter use additional control signals to readout reset and signal components in a
timely manner; wherein the signal input to SF2 is connected to what may be viewed as a
post stage node…),
control to disconnect one of the first capacitor element or the second capacitor element from the post-stage node (…as taught in [0336], for example, SE26 and SE27 are used to
connect elements C30 and C31 to common node in connection with SF2…), and
control to connect remaining of the one of the first capacitor element or the second capacitor element to the post-stage node (…wherein [0335-0338] teach signal readout from the sample and hold circuit by activating an amplification transistor SF2 and thereafter use additional control signals to readout reset and signal components in a timely manner; wherein the signal input to SF2 is connected to what may be viewed as a post stage node…), and
the post-stage reset transistor is configured to initialize a level of the post-stage node based on each of the first capacitor element and the second capacitor element that is disconnected from the post-stage node (…wherein, as diagramed in Fig. 15 t116 and t118 correspond to a timing wherein the switch SF30 is high thus to discharge parasitic capacitance; while control signals SE A-D (which represent SE7-SE12 are low thus disconnecting respective C30 and C31 from a connection to the gate of SF30…).
11. Regarding claim 9, an imaging device comprising:
a pre-stage circuit configured to generate a pixel signal (…[0135] teaches a pixel circuit 3a; Fig. 3…);
a sample-and-hold circuit configured to hold the pixel signal over a holding period (…[0135] teaches sample and hold circuit SH10 connected to circuit 3a; Fig. 3…), and
output the pixel signal a plurality of times within the holding period (…wherein
[0152] further teaches that the plurality of pixel signals are supplied to a subsequent
circuit after being sampled and held…);
a timing control circuit (…wherein [0120] teach a timing controller 20 which generates control signals of the imaging apparatus 100; Fig. 1…) configured to
sequentially designate, within the holding period, a plurality of gains with a control signal (…[0195] teaches gain detection circuit 401 (or 402) for a pixel signal from the sample and hold circuit (Fig. 6A or 7); as such high, middle, and low conversion gains; wherein these are sequentially processed in accordance with the function of the apparatus and exposure functions…)
an amplifier circuit configured to sequentially amplify the pixel signal with a gain of the plurality of gains (…wherein Ikuma, in [0112], teaches an amplification transistor SF1 which may be viewed as an amplification circuit along with corresponding amplification value that delivers a pixel signal with a particular amplification value; Ikuma also teaches SF2 and SEL_GS, as taught in [0176] and depicted in Fig. 3, being connected to vertical signal line 30A; and further in [0195], Ikuma teaches a first detection circuit 401 which detects what gain a pixel signal is correspondent to and transmits these as signal selection signals 407 to selection circuit 400. Further, signals 407 are provided to a voltage comparator 252 as gain selection signals, through vertical signal line 19B and amplification transistor SF30 (see [0196] and Fig. 12). Thus, voltage comparator 252 can be viewed as an amplifier circuit…);
generate, from an exposure operation, a plurality of pieces of image data based on the sequential amplification of the pixel signal (…wherein after the readout is performed, the signal is further processed and eventually a digital pixel signal is held in memory, in accordance with the schematic layout of Fig. 1…); and
a digital signal processing circuit configured to process image data wherein the image data includes pixel signals, including the pixel signal, in an array (…wherein Ikuma, in [0113], teaches AD converted pixel signals (with regards to pixel array 1; Fig. 1) being provided to signal processor 70 and 80; [0130] teaches an example of a calculation element 70 may perform…).
12. Regarding claim 12, claim 12 is rejected for reasons related to claim 1 (see claim 1 above).
Claim Rejections - 35 USC § 103
13. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ikuma et al. (US
2024/0121533 A1; further referred to as Ikuma) in view of Yen et al. (US 11153524 B1;
further referred to as Yen) and further view of Gyoten (WO2021145033A1).
15. Regarding claim 3, Ikuma teaches the solid-state imaging element according to claim 2 (see claim 2 above), further comprises:
a digital-to-analog converter configured to generate the ramp signal (…wherein [0127] teaches reference ramp signal generator 22 for generating a signal RAMP which is output to a voltage comparator 252 in each column AD circuit 25…);
a pixel array unit that includes a plurality of pixels (…wherein Fig. 1 teaches Pixel array 1…).
Ikuma doesn’t further teach wherein
a pixel of the plurality of pixels includes the pre-stage circuit and the sample-and-hold circuit (…however, Yen teaches a pixel circuit (Fig. 2), including elements of a photosensitive element and a sample and hold circuit, as taught in column 7-lines 33-38.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a pixel circuit can incorporate a sample
and hold circuitry as taught by Yen thereby reducing cost associated with stacked
configuration of a pixel…).
Further, though Ikuma teaches a comparator which compares a pixel signal with a reference ramp signal, Ikuma doesn’t explicitly teach wherein the comparator includes:
a differential amplifier circuit configured to
amplify a difference between a reference voltage and a voltage of a node (…however, Gyoten teaches a similar imaging device utilizing a comparator (400) including a differential amplifier circuit 430, as taught on pg. 8-lines 41-45 (Fig. 7); the differential amplifier amplifies a difference between a reference voltage VSH and a voltage of node 422, as taught on pg. 6- lines 25-27…), and
output the difference as a comparison result (…wherein the comparator
compares a reference signal RMP with an input of a signal Ain and produces an output
CMP as a result…);
a vertical-signal-line-side capacitor that is between the node and a vertical scanning line wherein the pixel is connected to the vertical scanning line (…wherein capacitor 416 is
connected between node 422 and a signal line 279 (Ain); Fig. 7…);
a ramp-side capacitor that is between the node and the digital-to-
analog converter (…wherein capacitor 421 is connected between node 422 and DAC 230 via signal line 239 (RMP), as taught on pg. 6- lines 46- 48…); and
a switch that is configured to change, based on the control signal, a capacitance ratio between the vertical-signal-line-side capacitor and the ramp-side capacitor, (…wherein pg. 6- lines 10- 17 teaches that one switch (of 411-415) is controlled so to change the capacity ratio
between VSL side capacitance and Ramp side capacitance (RMP), in accordance with a
capacitance ratio control signal Gctrl.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a capacitance ratio circuit could have
been implemented in conjunction with a differential amplifier, as taught by Gyoten, so
that different analog gains are grouped in accordance with corresponding capacitance
ratios wherein different analog gains may be retained in memory, thus to amplify a signal
accordingly…).
16. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ikuma et al.
(US2024/0121533 A1; further referred to as Ikuma) in view of Lee et al. (US 2002/0067303 A1; further referred to as Lee).
17. Regarding claim 4, Ikuma teaches the solid-state imaging element according to claim 2
(see claim 2 above), further comprising
a digital-to-analog converter configured to generate the ramp signal based on the control signal (…wherein Ikuma, taught in [0111], teaches reference ramp signal generator
22; Fig. 1…). Ikuma doesn’t further teach wherein
the timing control circuit is further configured to change, based on the control signal, a velocity at which the ramp signal fluctuates, using the control signal (…however, Lee teaches an image sensor with programmable multi-slope ADC having a programmable ramp generator 40; wherein a conversion cycle comprises a reference and data conversion stages, as taught in [0035]. In accordance with the depiction of Fig. 5, [0038] further teaches a reference conversion
stage takes place at time t2-t4 and a data conversion stage takes place at time t5 and at
time t6 the slope of ramp voltage is changed; wherein the time duration between t5-t6
may be greater than the duration of time t2-t4. Thus, the ramp signal changes for the two
stages of conversion.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that different slope transition point of
different lengths, as taught by Lee, could be implemented similarly in the ramp waveform
generator, as taught by Ikuma, so to enhance a resolution for low analog pixel values or
to increase dynamic range…).
18. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ikuma et al. (US
2024/0121533 A1; further referred to as Ikuma) in view of Yen et al. (US 11153524 B1;
further referred to as Yen).
19. Regarding claim 6, Ikuma teaches the solid-state imaging element according to claim 1
(see claim 1 above), further comprising
a post-stage circuit configured to supply the pixel signal to a vertical signal line (…Ikuma
teaches SF2 and SEL_GS, as taught in [0176] and depicted in Fig. 3, being connected to
vertical signal line 30A…).
Ikuma doesn’t further specify wherein
the amplifier circuit is further configured to supply the amplified pixel signal to the post-stage circuit (…however, Yen teaches a pixel circuit, Fig. 4, to include elements 42 and 41, which are read amplifiers particular to either a signal SN1 and SN2 of corresponding sample and hold circuits.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that amplifying circuits corresponding to a
plurality of sample and hold circuits, as taught by Yen, could be implemented thus to
assign particular offset values to different components of a pixel signal…).
20. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ikuma et al. (US
2024/0121533 A1; further referred to as Ikuma) in view of Mizuno (US 2021/0075974
A1).
21. Regarding claim 10, Ikuma teaches the imaging device according to claim 9 (see claim 9
above), further comprising
a set value holding unit configured to hold a value of a specific gain of the plurality of gains as a set value (…wherein Ikuma, in [0195] teaches a first detection circuit 401 which detects what gain a pixel signal is correspondent to and transmits these as signal selection signals 407 to selection circuit 400. Further, signals 407 are provided to a voltage comparator 252 as gain selection signals (403), through vertical signal line 19B and amplification transistor SF30 (see [0196] and Fig. 12)…),
based on a user operation, wherein
the amplifier circuit is further configured to amplify the pixel signal with the specific gain of the set value (…wherein Ikuma, in [0205], teaches that signal selection signals 407 are provided to comparator 252 of column AD circuit 25 as gain selection signals 403. Ikuma doesn’t specify to teach a user determined operation.
However, Mizuno teaches an endoscopic image processing unit wherein a
predetermined gain is used to increase a brightness level of pixels in a dark region of an
image. As such, based on a mode of observation set by a user, a brightness correction
unit may either perform or not perform to correct brightness using threshold values of
darkness and corresponding gain values for the pixels, as taught in [0120].
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a user determined brightness
correction, as taught by Mizuno, could be implemented in the gain level of pixel circuit
output as taught by Ikuma, thereby allowing a user to determine a gain level of pixel
adjustment so to make brighter a dark region of an image…).
22. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ikuma et al. (US
2024/0121533 A1; further referred to as Ikuma) in view of Niklaus et al. (US
2022/0321830 A1; further referred to as Niklaus).
23. Regarding claim 11, Ikuma teaches the imaging device according to claim 9 (see claim 9
above). Ikuma does not further teach the imaging device wherein
the digital signal processing circuit is further configured to perform machine learning, based on a specific number of pieces of image data of the plurality of pieces of image data (…however, Niklaus teaches an image processing system which uses machine learning including image data to perform a particular function of image processing, as taught in [0019].
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that machine learning in image processing,
as taught by Niklaus, could be implemented in a process of a combining circuit, as
taught by Ikuma, thus to optimize the means to perform an interpolation processing…).
Conclusion
24. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TWYLER HASKINS can be reached at (571)272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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