DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made wherein a domestic priority of this application is claimed under 35 U.S.C. 120. The PCT Application PCT/JP2023/006465, being filed on February 22, 2023.
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application filed on August 28, 2024.
Information Disclosure Statement
The information disclosure statements filed August 28,2024 and October 07, 2025 have been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered.
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 1, the limitation “a first laminate portion located on the first surface … a first mounting region located on a first outer surface on an opposite side to the first surface in the second insulation layer; a second mounting region located on the first outer surface to surround the first mounting region in the second insulation layer…in a frame-shaped region between an outer peripheral edge of the first mounting region and an outer peripheral edge of the second mounting region, a through- hole conductor configured to connect the first electrical conductor layer and the second electrical conductor layer is located across an edge of the opening” are indefinite and unclear.
Note that see figure 1, the first mounting region 31 represent by the electronic component 7 in figure 1, the second mounting region 32 represent by the stiffener 8 in figure 1. However, both of them underlying essential structure are missing in the claim.
Additionally, “the a through- hole conductor configured to connect the first electrical conductor layer and the second electrical conductor layer is located across an edge of the opening.” Is unclear or indefinite. Use of Configured to is improper. See figure 1, a through- hole conductor is already connected the first electrical conductor layer and the second electrical conductor layer is located across an edge of the opening; thefore, it does not have capacity to connect again.
Note that examiner broadly considers any region between outer peripheral edge region of a top surface of solder resist layer of the board and any middle region of a top surface of solder resist layer of the board would satisfy the limitation.
Appropriate correction is required.
Rejection of claims 2-13, claims 2-13 are rejected by the same reason applied to rejection of claim 1 above.
Rejection of claim 2, term “the through-hole conductors” lacks antecedent basis. Note that claim 1 discloses a through-hole conductor. And also, no relationship established between a through-hole conductor in claim 1 and through-hole conductors in claim 2. Therefore, claim is not clear.
Rejection of claim 3, term “the through-hole conductors” lacks antecedent basis. Note that claim 1 discloses a through-hole conductor. And also, no relationship established between a through-hole conductor in claim 1 and through-hole conductors in claim 2. Therefore, claim is not clear.
Similarly reason apply to term “a plurality of opening”.
Appropriate correction is required.
Rejection of claim 7, term “the through-hole conductors” lacks antecedent basis. Note that claim 1 discloses a through-hole conductor. And also, no relationship established between a through-hole conductor in claims 1 and 6 and through-hole conductors in claim 7. Therefore, claim is not clear.
Similarly reason apply to term “a plurality of opening”.
Appropriate correction is required.
Rejection of claim 11, term “each of the plurality of openings” lacks antecedent basis. Note that claim 1 discloses an opening. And also, no relationship established between an opening in claim 1 and each of a plurality of openings in claim 11. Therefore, claim is not clear.
Appropriate correction is required.
Rejection of claim 13, the limitation “wherein the first electrical conductor layer inside the opening” is not clear.
Claim 1 mentions that the solder resist layer having an opening from which a part of the first electrical conductor layer is exposed that interpreted as hole which shows part of the first electrical conductor layer.
While claim 13 mentions that wherein the first electrical conductor layer inside the opening.
The opening is an opening from which a part of the first electrical conductor layer is exposed covered by solder or the opening is an opening from which a part of the first electrical conductor layer is exposed filled by solder or the opening is where the first electrical conductor layer is filled.
It appears that two different structure provided for the opening wherein claim 13 appears to nullify the opening wherein claim 1.
Therefore, claim 13 is improper subject matter claimed.
Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102 which forms the basis for all rejections set forth in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, and 4 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) (whichever apply) as being anticipated by Ito et al. (US20160027724, herein referred to as Ito).
Rejection of claim 1, Ito (figures 1-3) discloses a wiring board comprising: a first insulation layer (1) having a first surface (a top surface of 1) and a second surface (a bottom surface of 1) located on an opposite side to the first surface; a first laminate portion located on the first surface and comprising insulation layers (insulation layers 3 on the top surface of 1); a second laminate portion located on the second surface and comprising insulation layers (insulation layers 3 on the bottom surface of 1); a second insulation layer located as an outermost layer of the insulation layers in the first laminate portion (top most layer insulation 3 of the insulation layers 3 on the top surface of 1); a third insulation layer located as an outermost layer of the insulation layers in the second laminate portion (bottom most layer insulation 3 of the insulation layers 3 on the top surface of 1); a first mounting region located on a first outer surface on an opposite side to the first surface in the second insulation layer (a first region covered by E); a second mounting region located on the first outer surface to surround the first mounting region in the second insulation layer (a second region covered by 9); a first electrical conductor layer having a planar shape and located on a second outer surface on an opposite side to the second surface in the third insulation layer (see one of conductor 10 on a second outer surface on an opposite side to the second surface in the third insulation layer 3) ; a second electrical conductor layer located on a second inner surface on the second surface side in the third insulation layer (see one of conductors located on a second inner surface on the second surface side in the third insulation layer 3); and a solder resist (12) covering the second outer surface of the third insulation layer and the first electrical conductor layer, and having an opening from which a part of the first electrical conductor layer is exposed (an opening exposed from the one the conductors 10) , wherein in a plane perspective view, in a frame-shaped region between an outer peripheral edge of the first mounting region and an outer peripheral edge of the second mounting region (see figure 1 where in the opening provided between E or any region passing through center of multiple 8 creating square or rectangular shape), a through- hole conductor s the first electrical conductor layer and the second electrical conductor layer is located across an edge of the opening (see a through hole conductor between the first and the second conductors, see figures).
Rejection of claims 4, Ito discloses the wiring board according to claim 1, wherein in a plane perspective view, the opening has a circular shape and the through-hole conductor has a circular shape (see rejection of claim 1 and figures).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of JP2015-076564 (cited reference), herein referred to as JP2015.
Rejection of claims 5-6, Ito discloses the wiring board according to claim 1, but fail to disclose wherein in a plane perspective view, the opening has a circular shape and the through-hole conductor has an arc shape (claim 5); and wherein in a plane perspective view, the opening has a circular shape and the through-hole conductor has a annular shape (claim 6).
JP2015 discloses selecting an annular shape or a crescent shape ("circular arc shape") as the via shape is also a well-known feature, as described in JP2015 (paragraph [0067], fig. 11).
It would have been obvious design choice to ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of Ito to have through hole conductor having specific shapes as mentioned in the JP2015 in order to pass electrical signal or current between opposite sides of the via conductor as well as limit or maintain current capacity.
Allowable Subject Matter
Claims 8-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Note that Claims 8-10 are rejected under USC 112, see rejection under USC 112 above.
Pertinent Prior Arts
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various wiring boards.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARESH PAGHADAL whose telephone number is (571)272-5251. The examiner can normally be reached 7:00AM-4:00PM, Monday - Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847
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