DETAILED ACTION
The response filed on August 07, 2026, is being examined.
Information Disclosure Statement
Applicants must continue to submit prior art references throughout the patent application. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claim 1, the limitation “the first mounting region located on a first outer surface on an opposite side to the first surface in the second insulation layer… a first electrical conductor layer having a planar shape and located on a second outer surface on an opposite side to the second surface in the third insulation layer… a second electrical conductor layer located on a second inner surface on the second surface side in the third insulation layer” are indefinite and unclear.
Note that the first surface and the second surface are part of the first insulation layer.
Correct structure appears to be:
The first mounting region is located on an outer surface of the second insulation layer opposite to an inner surface of the second insulation layer located toward the first surface of the first insulation layer;
a first electrical conductor layer having a planar shape and located on a second outer surface of the third insulation layer on an opposite side to a second inner surface of the third insulation layer toward the second surface of the first insulation layer.
a second electrical conductor layer located on a second inner surface of the third insulation layer.
Please clarify.
Appropriate correction is required.
Rejection of claims 2-13, claims 2-13 are rejected for the same reason applied to rejection of claim 1 above.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Note: The rejection under USC 102 and/or USC 103 below are given to advance prosecution; however, proper clarification is required under rejection of USC 112 above to consider the rejection under USC 102 and/or USC 103
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102 which forms the basis for all rejections set forth in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-9, 11 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) (whichever apply) as being anticipated by Ito et al. (US20160027724, herein referred to as Ito) or Fukushima et al. (US20140291005, herein referred to as Fukushima) or Iyoda et al. (US20230115650, herein referred to as Iyoda).
Rejection of claim 1, Ito (figures 1-3) or Fukushima (figures 1-3) or Iyoda (figures 1-3) discloses a wiring board comprising: a first insulation layer (an insulating layer 1 of Ito; or the core substrate 1 (insulating board) of Fukushima; or an insulating layer 20 of Iyoda) having a first surface (a top surface of 1 Ito; a top surface of 1 of Fukushima; or a top surface of 20 of Iyoda) and a second surface (a bottom surface of 1 of Ito; or a bottom surface of 1 of Fukushima; a bottom surface of 20 of Iyoda) located on an opposite side to the first surface; a first laminate portion located on the first surface and comprising insulation layers (insulation layers on the top surface of 1 of ito; or insulation layers on the top surface of 1 of Ito; insulation layers on the top surface of 20 of Ito ); a second laminate portion located on the second surface and comprising insulation layers (insulation layers 3 on the bottom surface of 1); a second insulation layer located as an outermost layer of the insulation layers in the first laminate portion (top most layer insulation of the insulation layers on the top surface of 1 of Ito; or top most layer insulation layer of the insulation layers on the top surface of 1 of Fukushima; or top most layer insulation layer of the insulation layers on the top surface of 20 of Iyoda ); a third insulation layer located as an outermost layer of the insulation layers in the second laminate portion (bottom most layer insulation 3 of the insulation layers 3 on the top surface of 1); a first mounting region located on a first outer surface of the second insulation layer to a surface of the second insulation layer toward the first surface of the first insulation layer (a first region encompassed by E1 or pads 28 in I Ito; or a first region X or a region encompassed by pads 5P and 5G (fig.5) in Fukushima; or a first region inside of a frame shaped region of pads 3a in Iyoda ); a second mounting region located on the first outer surface to surround the first mounting region in the second insulation layer (a second region of Ito encompassed by 29; or a second region Y or a region encompassed by pads 5s of Fukishima; or a region encompassed by pads 5s of Fukishima; or a second region outside of a frame shaped region of pads 3a in Iyoda ); a first electrical conductor layer having a planar shape and located on a second outer surface of the third insulation layer a surface of the third insulation layer toward the second surface of the first insulation layer (see conductor pads 10 on the bottom most insulation layer 3 exposed by solder resist 12 and between the first and the second regions when looking from top in Ito (see figure shown below in response to arguments); or see conductor pads 8 on bottom insulating layer exposed by solder resist and between the first and second regions in Fukushima; see conductor pads 3a on bottom insulating layer exposed by solder resist and between the first and second regions in Iyoma) ; a second electrical conductor layer located on a second inner surface of the third insulating la on the second surface side in the third insulation layer (see conductor pads located on a second inner surface on the second surface side in the bottom insulation layer toward the second surface of the first insulating layer of Ito Corresponding Vias and first conductor pads on second outer surface of the third insulation layer in Ito; or similarly see in Fukushima; or similarly see in Iyoda ); and a solder resist covering the second outer surface of the third insulation layer and the first electrical conductor layer, and having an opening from which a part of the first electrical conductor layer is exposed (an opening in solder resist which exposed a part of first conductor layer (a part of the conductor pads)) , wherein in a plane perspective view, in a frame-shaped region between an outer peripheral edge of the first mounting region and an outer peripheral edge of the second mounting region (see the region between the first region and the second region in Ito; or the region between the first region and the second region in Fukushima; or a frame shaped region of pads 3a not including region IV ), a through- hole conductor connects the first electrical conductor layer and the second electrical conductor layer is located across and intersects an edge of the opening (see a through hole conductor connects and located across the first and the second conductor layers, see figure of Ito; similarly see in Fukushima; or see in Iyoda ).
Rejection of claims 2, Ito or Fukushima or Iyoda discloses the wiring board according to claim 1, comprising a plurality of through-hole conductors including the through-hole conductor, wherein the plurality of wherein the through-hole conductors are located at point-symmetrical positions with respect to a center of the opening, the center acting as a point of symmetry (see vias in rejection of claim 1 and figures of Ito; or see vias in rejection of claim 1 and figures of Ito of Fukushima: additionally, it is known and obvious that cylinder via known in the art for connection between two conductive layers in third insulating layer (also as shown in core or first insulating layer having that in the other layer is obvious)).
Rejection of claims 3, Fukushima or Iyoda discloses the wiring board according to claim 1, wherein the frame- shaped region has a quadrilateral frame shape comprising four corner portions and four side portions in a plan view, the solder resist has a plurality of openings including the opening, a plurality of through-hole conductors including the through-hole conductor are located corresponding to the plurality of openings, respectively, the through-hole conductors comprise first through-hole conductors located in the corner portions of the quadrilateral frame-shape, and second through-hole conductors located in the side portions of the quadrilateral frame-shape, the first through-hole conductors are located along a first direction extending along a diagonal line connecting the corner portions, and the second through-hole conductors are located along a second direction perpendicular to the side portion that is in close proximity to the second through-hole conductors(see conductor vias in rejection of claim 1 and figures of Fukushima; or see conductor vias in rejection of claim 1 and figures of Iyoda).
Rejection of claims 4, Ito or Fukushima discloses the wiring board according to claim 1, wherein in a plane perspective view, the opening has a circular shape and the through-hole conductor has a circular shape (see rejection of claim 1 and figures of Ito; or see figures of Fukushima).
Rejection of claims 7, Fukushima or Iyoda discloses the wiring board according to claim 1, wherein the frame- shaped region has a quadrilateral frame shape comprising four corner portions and four side portions in a plan view, the solder resist has a plurality of openings including the opening, a plurality of through-hole conductors including the through-hole conductor are located corresponding to the plurality of openings, respectively, the through-hole conductors comprise first through-hole conductors located in the corner portions of the quadrilateral frame-shape, and second through-hole conductors located in the side portions of the quadrilateral frame-shape, the first through-hole conductors are located along a first direction extending along a diagonal line connecting the corner portions, and the second through-hole conductors are located along a second direction perpendicular to the side portion that is in close proximity to the second through-hole conductors(see conductor vias in rejection of claim 1 and figures of Fukushima; or see conductor vias in rejection of claim 1 and figures of Iyoda).
Rejection of claims 8, Iyoda discloses the wiring board according to claim 1, wherein in a plane perspective view, between an outer peripheral edge of the first mounting region and an inner peripheral edge of the second mounting region, when the opening located in the corner portion has a first length that is a length of the opening in the first direction, a second length that is a length of the opening in the second direction, a third length that is a length of the opening in a third direction orthogonal to the first direction, and a fourth length that is a length of the opening in a fourth direction orthogonal to the second direction, the third length is greater than the first length and the fourth length is greater than the second length (see edges of openings 4a in the figures of Iyoda).
Rejection of claims 9, Iyoda discloses the wiring board according to claim 1, but fails to disclose wherein each of a ratio between the first length and the third length, and a ratio between the second length and the fourth length is in a range from 1:3.15 to 1:5.
It is well known and old as well as examiner makes official notice that rectangular shape of opening have a ratio between the first length and the third length, and a ratio between the second length and the fourth length is in a range from 1:3.15 to 1:5. So that able to cover and contact area of longer rectangular pad of other electronic component for reliability.
Rejection of claims 11, Ito or Fukushima or Iyoda discloses the wiring board according to claim 1, wherein the solder resist has a plurality of openings including the opening, and each of the plurality of openings has the same area (see at least two openings in figures of Ito or Fukushima or Iyoda).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ito or Fukushima or Iyoda in view of JP2015-076564 (cited reference), herein referred to as JP2015.
Rejection of claims 5-6, Ito or Fukushima or Iyoda discloses the wiring board according to claim 1, but fail to disclose wherein in a plane perspective view, the opening has a circular shape and the through-hole conductor has an arc shape (claim 5); and wherein in a plane perspective view, the opening has a circular shape and the through-hole conductor has a annular shape (claim 6).
JP2015 discloses selecting an annular shape or a crescent shape ("circular arc shape") as the via shape is also a well-known feature, as described in JP2015 (paragraph [0067], fig. 11).
It would have been obvious design choice to ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of or Fukushima or Iyoda to have through hole conductor having specific shapes as mentioned in the JP2015 in order to pass electrical signal or current between opposite sides of the via conductor as well as limit or maintain current capacity.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Ito or Fukushima or Iyoda in view of Watanabe et al. (US7626829, herein referred to as Watanabe).
Rejection of claims 12, Ito or Fukushima or Iyoda discloses the wiring board according to claim 1, fails to disclose wherein the through-hole conductor has a length of at least 50 pm in a direction orthogonal to the edge of the opening.
Watanabe discloses the through-hole conductor has a length of at least 50 pm in a direction orthogonal to the edge of the opening (see length of via conductor is same as the thickness of the insulation base material is 20-600 micrometers, and see figure 3 of Watanabe) .
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of Ito to have through hole conductor length as taught by Watanabe so through hole conductor are able to contact conductor layer on both ends to transfer power, signal or information from one side to other side of the insulating layer.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ito or Fukushima or Iyoda in view of Tomoyuki et al. (JP2018186121 (cited reference), herein referred to as Tomoyuki).
Rejection of claims 13, Ito or Fukushima or Iyoda discloses the wiring board according to claim 1, an electronic component located in the first mounting region but fails to discloses one or more of limitations: a stiffener located in the second mounting region; and an external substrate comprising an electrode, wherein the first electrical conductor layer exposed from inside the opening and the electrode are connected to each other via a solder.
Tomoyuki discloses a stiffener located in the second mounting region; and an external substrate comprising an electrode, wherein the first electrical conductor layer exposed from inside the opening and the electrode are connected to each other via a solder (see figures 4-5 of ) .
It would have been obvious to ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of or Fukushima or Iyoda to have surface mount component on the wiring board as taught by Tomoyuki so electrical connection between electric components via circuit or wiring board and protect one of the electronic surface mount component via stiffener.
Allowable Subject Matter
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Note that Claims 8-10 are rejected under USC 112, see rejection under USC 112 above.
Response to Argument
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection (see new reference) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Response to argument with regard to Ito, applicant assessment with regard to a through-hole conductor appears to be incorrect; see figure shown below of Ito and match with 41, 42, and through hole conductor in figure 1 of applicant’s invention having same through hole conductor.
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Therefore, Applicant’s arguments are not persuasive.
Pertinent Prior Arts
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various wiring boards.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
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/PARESH PAGHADAL/ Primary Examiner, Art Unit 2847
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