DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2009/0140369).
Regarding claim 1, Lee discloses a semiconductor device (Figure 2), comprising: a semiconductor chip (Figure 2, reference 121); and a thermistor (Figure 2, reference 130) mounted on the semiconductor chip (Figure 2, reference 121), wherein the thermistor is mounted on an insulating substrate (Figure 2, reference 150) bonded to the semiconductor chip (Figure 2, reference 121), and the semiconductor chip (Figure 2, reference 121) and the thermistor (Figure 2, reference 130) are insulated from each other by the insulating substrate (Figure 2, reference 150), and formed on the insulating substrate (Figure 2, reference 121) is at least one pattern wiring leading an electrode (Figure 2, reference 141) of the thermistor (Figure 2, reference 130) outside of the thermistor (Figure 1, reference 130) in a plan view.
Regarding claim 2, Lee discloses wherein formed on the insulating substrate (Figure 2, reference 150) are the two pattern wirings (Figure 2, references 183 and 184) leading two electrodes (Figure 2, references 141 and 145) of the thermistor (Figure 2, reference 130) outside of the thermistor in a plan view, respectively.
Regarding claim 3, Lee discloses wherein an effective region of the semiconductor chip (Figure 2, reference 121 outer edge area) extends to a lower side of a position where the thermistor (Figure 2, reference 130) is mounted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0140369) in view of Schweikert et al (US 2020/0321262 A1).
Lee discloses all of the above claimed subject matter.
However, Lee does not disclose wherein the semiconductor chip is formed using SiC (claim 4).
Schweikert et al disclose wherein the semiconductor chip (Figure 1, reference 103) is formed using SiC (paragraphs 0017-0018).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Lee with the teachings of Schweikert et al to form a semiconductor chip with SiC because SiC, Si, SiGe, GaAs, GaN, are well known specific semiconductor materials used for semiconductor chips in the formation of semiconductor modules which may comprise AC/DC or DC/DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, logic integrated circuits, etc.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0140369) in view of Naka et al (US 2003/0113076 A1).
Lee discloses the above independently claimed subject matter.
However, Lee does not disclose wherein the semiconductor chip and the insulating substrate are bonded to each other by a bonding material containing Ag (claim 5) nor wherein the insulating substrate is formed by AlN (claim 6).
Naka et al discloses wherein the semiconductor chip (Figure 6, reference 10) and the insulating substrate (Figure 6, reference 27a) are bonded to each other by a bonding material (Figure 6, reference 28) containing Ag (paragraph 0094) and wherein the insulating substrate is formed by AlN (paragraph 0087).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Lee with the teachings of Naka et al for the purpose of bonding an insulating substrate to a semiconductor chip by using a silver paste because the silver paste material rarely cracks from the thermal strain occurring at the bonding portions of the electronic part whereby peeling-off of the chip parts can be prevented in semiconductor devices. Also, aluminum nitride as well as silicon carbide and silicon are material used as an insulating substrate because they have a thermal expansion coefficient similar to a thermal expansion coefficient of quartz or the like constituting an optical element such as a semiconductor laser chip or a photo diode chip, or the optical fiber in semiconductor devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
September 11, 2026
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