Prosecution Insights
Last updated: July 17, 2026
Application No. 18/842,462

METHODS AND APPARATUS OF DMRS SEQUENCE GENERATION

Non-Final OA §103
Filed
Aug 29, 2024
Priority
Apr 27, 2022 — nonprovisional of PCTCN2022089534
Examiner
PANCHOLI, RINA C
Art Unit
Tech Center
Assignee
Lenovo (United States) Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
502 granted / 584 resolved
+26.0% vs TC avg
Strong +23% interview lift
Without
With
+22.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
22 currently pending
Career history
608
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
83.1%
+43.1% vs TC avg
§102
1.9%
-38.1% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 584 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-20 received on 8/29/2024 have been examined, of which claims 1, 14-16 are independent. Claim Objections Claims 10 are objected to because of the following informalities: Claim 10 recites “Ue”, which appears to be typographical error for “UE”. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-3, 5-7, 10-12, 14-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al. (US 20210385038) in view of Yu et al. (US 20250119320) Regarding claim 1, Gao teaches a user equipment (UE) (device 900 in fig 9 implemented as terminal device 120, fig 1, para 127), comprising: at least one memory (memory 920, fig 9); and at least one processor (processor 910, fig 9) coupled with the at least one memory (fig 9) and configured to cause the UE (terminal device 120, fig 1) to: receive a configuration for Demodulation Reference Signal (DMRS) (para 43-45: the network device 110 determines (311) configurations for UL DMRS transmissions, and transmits (312) the determined configurations to the terminal device 120) that includes a first set of DMRS ports and a second set of DMRS ports (para 43-45: the configurations may also indicate one or more DMRS ports to be used for UL DMRS transmission, the configurations may indicate a plurality of parameters related to the generation of DMRS sequences); generate DMRS sequences for the first and second sets of DMRS ports (para 46-48: in response to receiving the configurations for UL DMRS transmission, the terminal device 120 may generate (313) one or more DMRS sequences based on the configurations, then, the terminal device 120 may transmit (314) the generated one or more DMRS sequences to the network device 110, the terminal device 120 may need to generate different DMRS sequences for the DMRS ports from different CDM groups, and the terminal device 120 may need to transmit the different DMRS sequences at the same time). Gao teaches the multiple DMRS ports configuration, ports corresponding to different CDM groups and generating different DMRS sequences for different CDM groups and DMRS ports. Gao further teaches in fig 2a-d and para 37, the type 1 DMRS ports 0-7 and type 2 DMRS ports 0-11. However, the reference does not teach type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23. Yu is directed to generating DMRS sequence and mapping to resources corresponding to CDM group (abstract). Yu further teaches wherein the first set of DMRS ports comprises type 1 DMRS ports 0-7 or type 2 DMRS ports 0-11 (fig 4, two symbols, CDM group 0 includes DMRS ports {p0, p1, p4, p5, p8, p9, p12, p13}, para 212) and the second set of DMRS ports comprises type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23 (fig 4, two symbols, the CDM group 1 includes DMRS ports {p2, p3, p6, p7, p10, p11, p14, p15}, para 212; para 215: when the foregoing embodiment of this application is applied to the DMRS whose configuration type is the type 1 DMRS, orthogonality between 16 DMRS ports may be supported without increasing DMRS overheads). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine DMRS sequence generation and transmission as taught by Gao with DMRS CDM groups with additional ports as taught by Yu for the benefit of reducing inter-layer interference between DMRSs as taught by Yu in para 215. Regarding claim 14, Gao teaches a base station (device 900 in fig 9 implemented as network device 110, fig 1, para 127), comprising: at least one memory (memory 920, fig 9); and at least one processor (processor 910, fig 9) coupled with the at least one memory (fig 9) and configured to cause the base station (network device 110, fig 1) to: transmit a configuration for Demodulation Reference Signal (DMRS) (para 43-45: the network device 110 determines (311) configurations for UL DMRS transmissions, and transmits (312) the determined configurations to the terminal device 120) that supports a first set of DMRS ports and a second set of DMRS ports (para 43-45: the configurations may also indicate one or more DMRS ports to be used for UL DMRS transmission, the configurations may indicate a plurality of parameters related to the generation of DMRS sequences); and generate DMRS sequences for the first and second sets of DMRS ports (para 46-48: in response to receiving the configurations for UL DMRS transmission, the terminal device 120 may generate (313) one or more DMRS sequences based on the configurations, then, the terminal device 120 may transmit (314) the generated one or more DMRS sequences to the network device 110, the terminal device 120 may need to generate different DMRS sequences for the DMRS ports from different CDM groups, and the terminal device 120 may need to transmit the different DMRS sequences at the same time). Gao teaches the multiple DMRS ports configuration, ports corresponding to different CDM groups and generating different DMRS sequences for different CDM groups and DMRS ports. Gao further teaches in fig 2a-d and para 37, the type 1 DMRS ports 0-7 and type 2 DMRS ports 0-11. However, the reference does not teach type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23. Yu is directed to generating DMRS sequence and mapping to resources corresponding to CDM group (abstract). Yu further teaches wherein the first set of DMRS ports comprises type 1 DMRS ports 0-7 or type 2 DMRS ports 0-11 (fig 4, two symbols, CDM group 0 includes DMRS ports {p0, p1, p4, p5, p8, p9, p12, p13}, para 212) and the second set of DMRS ports comprises type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23 (fig 4, two symbols, the CDM group 1 includes DMRS ports {p2, p3, p6, p7, p10, p11, p14, p15}, para 212; para 215: when the foregoing embodiment of this application is applied to the DMRS whose configuration type is the type 1 DMRS, orthogonality between 16 DMRS ports may be supported without increasing DMRS overheads). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine DMRS sequence generation and transmission as taught by Gao with DMRS CDM groups with additional ports as taught by Yu for the benefit of reducing inter-layer interference between DMRSs as taught by Yu in para 215. Regarding claim 15, Gao teaches a method performed by a user equipment (UE) (fig 3, 7: method for RS/DMRS transmission), the method comprising: receiving a configuration for Demodulation Reference Signal (DMRS) (para 43-45: the network device 110 determines (311) configurations for UL DMRS transmissions, and transmits (312) the determined configurations to the terminal device 120) that supports a first set of DMRS ports and a second set of DMRS ports (para 43-45: the configurations may also indicate one or more DMRS ports to be used for UL DMRS transmission, the configurations may indicate a plurality of parameters related to the generation of DMRS sequences); and generating DMRS sequences for the first and second sets of DMRS ports (para 46-48: in response to receiving the configurations for UL DMRS transmission, the terminal device 120 may generate (313) one or more DMRS sequences based on the configurations, then, the terminal device 120 may transmit (314) the generated one or more DMRS sequences to the network device 110, the terminal device 120 may need to generate different DMRS sequences for the DMRS ports from different CDM groups, and the terminal device 120 may need to transmit the different DMRS sequences at the same time). Gao teaches the multiple DMRS ports configuration, ports corresponding to different CDM groups and generating different DMRS sequences for different CDM groups and DMRS ports. Gao further teaches in fig 2a-d and para 37, the type 1 DMRS ports 0-7 and type 2 DMRS ports 0-11. However, the reference does not teach type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23. Yu is directed to generating DMRS sequence and mapping to resources corresponding to CDM group (abstract). Yu further teaches wherein the first set of DMRS ports comprises type 1 DMRS ports 0-7 or type 2 DMRS ports 0-11 (fig 4, two symbols, CDM group 0 includes DMRS ports {p0, p1, p4, p5, p8, p9, p12, p13}, para 212) and the second set of DMRS ports comprises type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23 (fig 4, two symbols, the CDM group 1 includes DMRS ports {p2, p3, p6, p7, p10, p11, p14, p15}, para 212; para 215: when the foregoing embodiment of this application is applied to the DMRS whose configuration type is the type 1 DMRS, orthogonality between 16 DMRS ports may be supported without increasing DMRS overheads). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine DMRS sequence generation and transmission as taught by Gao with DMRS CDM groups with additional ports as taught by Yu for the benefit of reducing inter-layer interference between DMRSs as taught by Yu in para 215. Regarding claim 16, Gao teaches a processor for wireless communication (device 900 in fig 9 implemented as terminal device 120, fig 1, para 127; here, the term processor comprising controller and memory is interpreted as device comprising processor (or controller) and memory), comprising: at least one controller (processor 910, fig 9) coupled with at least one memory (memory 920, fig 9) and configured to cause the processor (terminal device 120, fig 1) to: receive a configuration for Demodulation Reference Signal (DMRS) (para 43-45: the network device 110 determines (311) configurations for UL DMRS transmissions, and transmits (312) the determined configurations to the terminal device 120) that includes a first set of DMRS ports and a second set of DMRS ports (para 43-45: the configurations may also indicate one or more DMRS ports to be used for UL DMRS transmission, the configurations may indicate a plurality of parameters related to the generation of DMRS sequences); and generate DMRS sequences for the first and second sets of DMRS ports (para 46-48: in response to receiving the configurations for UL DMRS transmission, the terminal device 120 may generate (313) one or more DMRS sequences based on the configurations, then, the terminal device 120 may transmit (314) the generated one or more DMRS sequences to the network device 110, the terminal device 120 may need to generate different DMRS sequences for the DMRS ports from different CDM groups, and the terminal device 120 may need to transmit the different DMRS sequences at the same time). Gao teaches the multiple DMRS ports configuration, ports corresponding to different CDM groups and generating different DMRS sequences for different CDM groups and DMRS ports. Gao further teaches in fig 2a-d and para 37, the type 1 DMRS ports 0-7 and type 2 DMRS ports 0-11. However, the reference does not teach type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23. Yu is directed to generating DMRS sequence and mapping to resources corresponding to CDM group (abstract). Yu further teaches wherein the first set of DMRS ports comprises type 1 DMRS ports 0-7 or type 2 DMRS ports 0-11 (fig 4, two symbols, CDM group 0 includes DMRS ports {p0, p1, p4, p5, p8, p9, p12, p13}, para 212) and the second set of DMRS ports comprises type 1 DMRS ports 8-15 or type 2 DMRS ports 12-23 (fig 4, two symbols, the CDM group 1 includes DMRS ports {p2, p3, p6, p7, p10, p11, p14, p15}, para 212; para 215: when the foregoing embodiment of this application is applied to the DMRS whose configuration type is the type 1 DMRS, orthogonality between 16 DMRS ports may be supported without increasing DMRS overheads). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine DMRS sequence generation and transmission as taught by Gao with DMRS CDM groups with additional ports as taught by Yu for the benefit of reducing inter-layer interference between DMRSs as taught by Yu in para 215. Regarding claim 2 and 17, Gao further teaches to receive a configuration for enabling low Peak-to-Average Power Ratio (PAPR) DMRS sequence (para 49: for DMRS type 1, if the rank is one, there will be no PAPR issue, if the rank is greater than one but the DMRS ports indicated in the DMRS port field of the DCI come from a same CDM group, there will still be no PAPR issue; in para 40, the issue of higher PAPR is discussed, thus no PAPR issue in para 49 is considered as lower PAPR for DMRS sequence). Regarding claim 3 and 18, Gao further teaches wherein the first set of DMRS ports are from a first set of Code-Division Multiplexing (CDM) groups, and the second set of DMRS ports are grouped into the first set of CDM groups (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 4, 5}, and CDM group 1 may include some or all of the DMRS ports {2, 3, 6, 7}); and the at least one processor is configured to cause the UE to generate two DMRS sequences for each CDM group in the first set of CDM groups (para 51: the terminal device 120 may need to generate two different DMRS sequences for CDM groups 0 and 1 respectively. For example, in FIG. 4, the terminal device 120 may generate a first DMRS sequence for CDM group 0, and transmit the first DMRS sequence over DMRS port 0. The terminal device 120 may generate a second DMRS sequence for CDM group 1, and transmit the second DMRS sequence over DMRS port 1, where the second DMRS sequence is different from the first DMRS sequence). Regarding claim 5 and 20, Gao further teaches wherein for DMRS type 1, the first set of CDM groups comprises CDM group 0 and CDM group 1 (para 45: FIGS. 2A and 2B, for DMRS type 1, up to two CDM groups can be used. That is, the index of a CDM group can be 0 or 1), where CDM group 0 includes DMRS ports 0, 1, 4, 5, 8, 9, 12, 13; and CDM group 1 includes DMRS ports 2, 3, 6, 7, 10, 11, 14, 15 (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 4, 5}, and CDM group 1 may include some or all of the DMRS ports {2, 3, 6, 7}; here, the claim does not limit if the CDM group consists of all the indicated ports, thus the reference teaching the CDM group that includes the ports indicated between 0 to 7 teaches the limitation). It is noted that Yu teaches the DMRS ports 0-15 for DMRS type 1. Thus, Yu also teaches wherein for DMRS type 1 (para 207: a DMRS whose configuration type is the first configuration type (Type 1 DMRS) is used), the first set of CDM groups comprises CDM group 0 and CDM group 1, where CDM group 0 includes DMRS ports 0, 1, 4, 5, 8, 9, 12, 13; and CDM group 1 includes DMRS ports 2, 3, 6, 7, 10, 11, 14, 15 (para 212: the CDM group 0 includes DMRS ports {p0, p1, p4, p5, p8, p9, p12, p13} and the CDM group 1 includes DMRS ports {p2, p3, p6, p7, p10, p11, p14, p15}). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine DMRS sequence generation and transmission as taught by Gao with DMRS CDM groups with additional ports as taught by Yu for the benefit of reducing inter-layer interference between DMRSs as taught by Yu in para 215. Regarding claim 6, Gao further teaches wherein for DMRS type 2, the first set of CDM groups comprises CDM group 0, CDM group 1 and CDM group 2 (para 45: fig. 2C and 2D, for DMRS type 2, up to three CDM groups can be used, the index of a CDM group can be 0, 1 or 2), where CDM group 0 includes DMRS ports 0, 1, 6, 7, 12, 13, 18, 19; CDM group 1 includes DMRS ports 2, 3, 8, 9, 14, 15, 20, 21; and CDM group 2 includes DMRS ports 4, 5, 10, 11, 16, 17, 22, 23 (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 6, 7}, CDM group 1 may include some or all of the DMRS ports {2, 3, 8, 9}, and CDM group 2 may include some or all of the DMRS ports {4, 5, 10, 11}; here, the claim does not limit if the CDM group consists of all the indicated ports, thus the reference teaching the CDM group that includes the ports indicated between 0 to 11 teaches the limitation). Regarding claim 7, Gao further teaches wherein the first set of DMRS ports are from a first set of CDM groups, and the second set of DMRS ports are grouped into a second set of CDM groups (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 4, 5}, and CDM group 1 may include some or all of the DMRS ports {2, 3, 6, 7}); and the at least one processor is configured to cause the UE to generate an additional DMRS sequence for each CDM group in the second set of CDM groups, different from a corresponding DMRS sequence in the first set of CDM groups (para 51: the terminal device 120 may need to generate two different DMRS sequences for CDM groups 0 and 1 respectively. For example, in FIG. 4, the terminal device 120 may generate a first DMRS sequence for CDM group 0, and transmit the first DMRS sequence over DMRS port 0. The terminal device 120 may generate a second DMRS sequence for CDM group 1, and transmit the second DMRS sequence over DMRS port 1, where the second DMRS sequence is different from the first DMRS sequence). Regarding claim 10, Gao further teaches wherein the first set of DMRS ports are from a first set of CDM groups, and the second set of DMRS ports are grouped into the first set of CDM groups (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 4, 5}, and CDM group 1 may include some or all of the DMRS ports {2, 3, 6, 7}); and the at least one processor is configured to cause the Ue to generate one sequence r(m) for all DMRS ports in each CDM group in the first set of CDM groups, where m is a list of nonnegative integers starting from zero (para 51: the terminal device 120 may need to generate two different DMRS sequences for CDM groups 0 and 1 respectively. For example, in FIG. 4, the terminal device 120 may generate a first DMRS sequence for CDM group 0, and transmit the first DMRS sequence over DMRS port 0. The terminal device 120 may generate a second DMRS sequence for CDM group 1, and transmit the second DMRS sequence over DMRS port 1, where the second DMRS sequence is different from the first DMRS sequence; here, two sequences indicate one sequence for all ports in respective CDM group, where there are two groups). Regarding claim 11, Gao further teaches wherein for DMRS type 1, the first set of CDM groups comprises CDM group 0 and CDM group 1 (para 45: FIGS. 2A and 2B, for DMRS type 1, up to two CDM groups can be used. That is, the index of a CDM group can be 0 or 1), where CDM group 0 includes DMRS ports 0, 1, 4, 5, 8, 9, 12, 13; and CDM group 1 includes DMRS ports 2, 3, 6, 7, 10, 11, 14, 15 (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 4, 5}, and CDM group 1 may include some or all of the DMRS ports {2, 3, 6, 7}; here, the claim does not limit if the CDM group consists of all the indicated ports, thus the reference teaching the CDM group that includes the ports indicated between 0 to 7 teaches the limitation); and wherein for DMRS type 2, the first set of CDM groups comprises CDM group 0, CDM group 1 and CDM group 2 (para 45: fig. 2C and 2D, for DMRS type 2, up to three CDM groups can be used, the index of a CDM group can be 0, 1 or 2), where CDM group 0 includes DMRS ports 0, 1, 6, 7, 12, 13, 18, 19; CDM group 1 includes DMRS ports 2, 3, 8, 9, 14, 15, 20, 21; and CDM group 2 includes DMRS ports 4, 5, 10, 11, 16, 17, 22, 23 (para 45: CDM group 0 may include some or all of the DMRS ports {0, 1, 6, 7}, CDM group 1 may include some or all of the DMRS ports {2, 3, 8, 9}, and CDM group 2 may include some or all of the DMRS ports {4, 5, 10, 11}; here, the claim does not limit if the CDM group consists of all the indicated ports, thus the reference teaching the CDM group that includes the ports indicated between 0 to 11 teaches the limitation). It is noted that Yu teaches the DMRS ports 0-15 for DMRS type 1. Thus, Yu also teaches wherein for DMRS type 1 (para 207: a DMRS whose configuration type is the first configuration type (Type 1 DMRS) is used), the first set of CDM groups comprises CDM group 0 and CDM group 1, where CDM group 0 includes DMRS ports 0, 1, 4, 5, 8, 9, 12, 13; and CDM group 1 includes DMRS ports 2, 3, 6, 7, 10, 11, 14, 15 (para 212: the CDM group 0 includes DMRS ports {p0, p1, p4, p5, p8, p9, p12, p13} and the CDM group 1 includes DMRS ports {p2, p3, p6, p7, p10, p11, p14, p15}). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine DMRS sequence generation and transmission as taught by Gao with DMRS CDM groups with additional ports as taught by Yu for the benefit of reducing inter-layer interference between DMRSs as taught by Yu in para 215. Regarding claim 12, Gao further teaches wherein the sequence r(m) has a first half being the DMRS sequence for DMRS ports of the CDM group in the first set of DMRS ports, and a second half being the DMRS sequence for DMRS ports of the CDM group in the second set of DMRS ports (para 48: the terminal device 120 may need to generate different DMRS sequences for the DMRS ports from different CDM groups, and the terminal device 120 may need to transmit the different DMRS sequences at the same time; here, the two sequences transmitted at the same time is considered for first half being one sequence for one CDM group and the other half being the other sequence for another CDM group). Allowable Subject Matter Claims 4, 8-9, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RINA C PANCHOLI whose telephone number is (571)272-2679. The examiner can normally be reached M-F 7:30am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chirag Shah can be reached on 571-272-3144. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RINA C PANCHOLI/Primary Examiner, Art Unit 2477 6/22/2026
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Prosecution Timeline

Aug 29, 2024
Application Filed
Jun 25, 2026
Non-Final Rejection mailed — §103 (current)

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