DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species V [figures 27-30d, corresponding to claims 1-2, 5-6, 8-14, 16-17, 19-20, & 22-24] in the reply filed on 7/17/2026 is acknowledged. The traversal is on the ground(s) that Tsai lacks a special technical feature [Remarks: pg. 9, 2nd – last para.]. This is not found persuasive because the Applicant argues two opposing sides while the claim only states two sides along the column direction.
Further claim 3 claims that first signal line and the second signal line, which corresponds to elements 91 and 92, are located on different conductive layers. This limitation corresponds to non-elected species II. Elected species V utilizes element 93 from a current row and a previous row to control emission [see para. 225 of pg pub of instant application, Species V being the 2SD implementation of Species IV]. Thus, claims 3-4 are withdrawn.
Claims 3-4 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/17/2026.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/26/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 13-14, 16-17, 22, & 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20200066212).
As to claim 1, Kim discloses a display substrate [figs 5 & 8 & para. 130-131] comprising a plurality of circuit units (pixel circuits pxij_a) [figs. 5 & 8] constituting a plurality of unit rows and a plurality of unit columns [figs. 5 & 8 & para. 53 & 105], at least one circuit unit comprises a pixel drive circuit (first transistor m1, fifth transistor m5, & sixth transistor m6) [figs. 5 & 8 & para. 90 & 94-95] and at least one control line (first emission line ei & second emission line e(i-1)) [figs. 5 & 8 & para. 94-95] configured to provide a light emitting control signal (first emission line ei & second emission line e(i-1)) [figs. 5-7] to the pixel drive circuit;
in at least one circuit unit, the pixel drive circuit at least comprises a drive transistor (first transistor m1) [figs. 5 & 8 & para. 90], a first light emitting control transistor (fifth transistor m5) [figs. 5 & 8 & para. 94], and a second light emitting control transistor (sixth transistor m6) [figs. 5 & 8 & para. 95], wherein a first electrode of the first light emitting control transistor is connected to a first power supply line (first power voltage line elvdd, fifth transistor m5) [figs. 5 & 8 & para. 94], a second electrode of the first light emitting control transistor is connected to a first electrode of the drive transistor (connection between first transistor m1 & fifth transistor m5) [figs. 5 & 8 & para. 94], and a first electrode of the second light emitting control transistor is connected to a second electrode of the drive transistor (connection between sixth transistor m6 & first transistor m1) [figs. 5 & 8 & para. 95];
the first light emitting control transistor and the second light emitting control transistor are connected to different control lines (fifth transistor m5 utilizing first emission line ei & sixth transistor m6 utilizing second emission line e(i-1)) [figs. 5-7 & para. 94-95], and the first light emitting control transistor and the second light emitting control transistor are respectively disposed at two sides of the drive transistor in a unit column direction (fifth transistor m5 & sixth transistor m6 opposing sides of first transistor m1) [fig. 8].
As to claim 2, Kim discloses the display substrate according to claim 1, wherein the at least one control line comprises a first signal line (fifth transistor m5 utilizing first emission line ei) [figs. 5-7 & para. 94] and a second signal line (sixth transistor m6 utilizing second emission line e(i-1)) [figs. 5-7 & para. 95], and the first light emitting control transistor is connected to the first signal line (fifth transistor m5 utilizing first emission line ei) [figs. 5-7 & para. 94] and the second light emitting control transistor is connected to the second signal line (sixth transistor m6 utilizing second emission line e(i-1)) [figs. 5-7 & para. 95], and the first signal line and the second signal line are respectively disposed at two sides of the drive transistor in the unit column direction (first emission line ei & second emission line e(i-1)) [fig. 8].
As to claim 13, Kim discloses the display substrate according to claim 1,wherein the at least one circuit unit further comprises a first initial signal line (first initialization voltage line vint1) [figs. 5 & 8] extending along a unit row direction and a first connection line (drain electrode de4 of fourth transistor m4) [figs. 5 & 8] extending along the unit column direction, the first initial signal line is configured to provide a first initial signal to the pixel drive circuit (first initialization voltage line vint1) [figs. 5 & 8], the first initial signal line and the first connection line are connected to form a net-like connecting structure for transmitting the first initial signal (drain electrode de4 of fourth transistor m4 connected to first initialization voltage line vint1) [figs. 5 & 8].
As to claim 14, Kim discloses the display substrate according to claim 13, wherein an orthographic projection of the first connection line on a plane of the display substrate is not overlapped with an orthographic projection of a gate electrode of the drive transistor on the plane of the display substrate (gate electrode ge1 for first transistor m1 not overlapped with drain electrode de4 of fourth transistor m4) [figs. 5 & 8]; or
wherein the pixel drive circuit further comprises a compensation transistor, an active layer of the compensation transistor and an active layer of the drive transistor are connected to each other by an active connection line, an orthographic projection of the first connection line on the plane of the display substrate and an orthographic projection of the active connection line on the plane of the display substrate are at least partially not overlapped.
As to claim 16, Kim discloses the display substrate according to claim 1,wherein the at least one circuit unit further comprises a second initial signal line (second initialization voltage line vint2) [figs. 5 & 8] extending along a unit row direction and a second connection line (drain electrode de7 of seventh transistor m7) [figs. 5 & 8] extending along the unit column direction, the second initial signal line is configured to provide a second initial signal to the pixel drive circuit (second initialization voltage line vint2) [figs. 5 & 8], the second initial signal line and the second connection line are connected to form a net-like connecting structure for transmitting the second initial signal (second initialization voltage line vint2 connected to drain electrode de7 of seventh transistor m7) [figs. 5 & 8].
As to claim 17, Kim discloses the display substrate according to claim 16, wherein an orthographic projection of the second connection line on a plane of the display substrate is not overlapped with an orthographic projection of a gate electrode of the drive transistor on the plane of the display substrate (drain electrode de7 of seventh transistor m7notoverlapped with gate electrode ge1 of first transistor m1) [fig. 8]; or
wherein the pixel drive circuit further comprises a compensation transistor, an active layer of the compensation transistor and an active layer of the drive transistor are connected to each other by an active connection line, an orthographic projection of the second connection line on a plane of the display substrate and an orthographic projection of the active connection line on the plane of the display substrate are at least partially not overlapped.
As to claim 22, Kim discloses the display substrate of claim 1, wherein the pixel drive circuit further comprises a storage capacitor (storage capacitor cst) [figs. 5 & 8] and a first capacitor (parasitic capacitance between elvdd & drain electrode de5 of fifth transistor) [figs. 8-9];
the storage capacitor comprises a first plate (one electrode le) [figs. 8-9 & para. 137-139] and a second plate (other electrode ue) [figs. 8-9 & para. 137-139], an orthographic projection of the first plate on a plane of the display substrate is at least partially overlapped with an orthographic projection of the second plate on the plane of the display substrate [figs. 8-9 & para. 137-139], the first plate serves as a gate electrode of the drive transistor (one electrode le & first gate electrode ge1 of first transistor m1) [figs. 8-9 & para. 137-139], and the second plate is connected to the first power supply line (elvdd & other electrode ue) [figs. 8-9 & para. 137-139];
the first capacitor comprises a third plate and a fourth plate, an orthographic projection of the third plate on the plane of the display substrate is at least partially overlapped with an orthographic projection of the fourth plate on the plane of the display substrate, the third plate is respectively connected to the first electrode of the drive transistor and the second electrode of the first light emitting control transistor, and the fourth plate is connected to the first power supply line (parasitic capacitance between electrode of elvdd & drain electrode de5 of fifth transistor m5) [fig. 8].
As to claim 24, Kim discloses a display apparatus [figs. 1 & 5 abstract & para. 53 & 88-89], comprising a display substrate [figs. 5 & 8 & para. 130-131] according to claim 1.
Allowable Subject Matter
Claims 5-6, 8-12, 19-20, & 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gao et al. (US 20210280132).
Liu et al. (US 20210359075).
Lee et al. (US 20160322450).
Diao et al. (US 20210193780).
Yu et al. (US 20180204889).
Jeon et al. (US 20180144684).
Kim et al. (US 20190096335).
Park et al. (US 20200211476).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
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/DAVID TUNG/Primary Examiner, Art Unit 2622
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