Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 14, 18, and 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al., US PGPub 2009/0249001, hereafter “Narayanan,” in view of Ould-Ahmed-Vall, US PGPub 2020/0409697, hereafter “Ould.”
With respect to claim 1, Narayanan teaches an apparatus for a computer system, the apparatus comprising circuitry configured to:
provide an interface for accessing persistent memory provided by persistent memory circuitry of the computer system from one or more software applications (par. 127, an application programming interface is used for software applications to perform writes. The storage that is written to is persistent memory, as described in pars. 31-32);
Narayanan fails to disclose wherein the interface is configured to provide access via at least a first offloading circuitry and a second offloading circuitry of the computer system; select a low-level library of the first or second offloading circuitry depending on which of the first and second offloading circuitry is used for accessing the persistent memory, resulting in a selected low-level library and a corresponding selected offloading circuitry; translate instructions for performing operations on the persistent memory into corresponding instructions suitable for the selected offloading circuitry; provide the corresponding instructions to the selected offloading circuitry via the selected low-level library; and provide the access to the persistent memory via the selected offloading circuitry. Ould teaches:
wherein the interface is configured to provide access via at least a first offloading circuitry and a second offloading circuitry of the computer system (par. 152 and fig. 12A, the helper cores 1201A and 1201C are the first and second offloading circuitry);
select a low-level library of the first or second offloading circuitry depending on which of the first and second offloading circuitry is used for accessing the persistent memory, resulting in a selected low-level library and a corresponding selected offloading circuitry (par. 140 and fig. 11, first binary code 1106 is generated for processor 1116, and alternate instruction binary code 1110 is generated for the alternate processor 1114. These processors correspond to helper cores 1201A and 1201C of fig. 12A, the first and second offloading circuitry);
translate instructions for performing operations on the persistent memory into corresponding instructions suitable for the selected offloading circuitry (pars. 139-140 and 146, translating the instructions into the binary code for either processor 1114 or 1116);
provide the corresponding instructions to the selected offloading circuitry via the selected low-level library (pars. 39-140 and 146, the binary code is provided for the particular ISA); and
provide the access to the persistent memory via the selected offloading circuitry (pars. 152-153, the helper cores access memory).
It would have been obvious to one of ordinary skill in the art, having the teachings of Narayanan and Ould before him before the earliest effective filing date, to modify the memory access system of Narayanan with the memory access method of Ould, as the translation into a specific binary code allows a processor or other electronic device that does not have a first instruction set processor or core to execute the binary code, as taught by Ould in par. 140.
With respect to claim 2, Narayanan and Ould teach the limitations of the parent claim. Narayanan further teaches the apparatus according to claim 1, wherein the circuitry is configured to expose the access to the persistent memory as a virtual block-level device or a byte-addressable device (par. 132, the API provides read and write access to memory using byte ranges (byte-addressable)).
With respect to claim 3, Narayanan and Ould teach the limitations of the parent claim. Narayanan further teaches the apparatus according to claim 1, wherein the circuitry is configured to provide the access to the persistent memory via asynchronous interface calls (par. 153, asynchronous I/O calls).
With respect to claim 4, Narayanan and Ould teach the limitations of the parent claims. Ould further teaches the apparatus according to claim 3, wherein the circuitry is configured to translate the instructions for performing operations on the persistent memory into corresponding instructions for the offloading circuitry (par. 140, the instructions are translated into binary code for the particular processor’s instruction set architecture). Ould doesn’t specifically describe the instructions as “asynchronous.” Narayanan teaches asynchronous instructions (par. 153).
With respect to claim 5, Narayanan and Ould teach the limitations of the parent claims. Narayanan further teaches the apparatus according to claim 4, wherein the circuitry is configured to translate callback notifications issued by the offloading circuitry into callback notifications for the one or more software applications (pars. 152-153, the shim layer operates to translate communication for applications, including the completion callback, the callback notification of the claim).
With respect to claim 14, Narayanan and Ould teach all limitations of the parent claim, Narayanan further teaches the apparatus according to claim 1, wherein the circuitry is configured to provide the interface and/or translate the instructions by providing a software framework for accessing the persistent memory (par. 127, the APIs both provide the interface and provide the software framework for translating instructions).
Claim 18 is a device for a computer system that corresponds to claim 1, and is rejected using similar logic.
Claims 20 and 22-24 are a method for a computer system that corresponds to claims 1-4, and are rejected using similar logic.
Claim 21 is a non-transitory machine readable storage medium including a program code for performing the method of claim 20 when the program code is executed on a computer, a processor, or a programmable hardware component, and is rejected using similar logic as claims 1 and 20.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan and Ould as applied to claim 1 above, and further in view of Zyulkyarov et al., US PGPub 2015/0227469, hereafter “Zyulkyarov.”
With respect to claim 6, Narayanan and Ould teach all limitations of the parent claim, but fail to specifically disclose “memory management.” Zyulkyarov further teaches the apparatus according to claim 1, wherein the circuitry is configured to perform memory management for accessing the persistent memory (par. 57, the memory management unit for translating virtual memory addresses).
It would have been obvious to one of ordinary skill in the art, having the teachings of Narayanan, Ould and Zyulkyarov, to modify the memory access system of Narayanan and Ould with the memory access system of Zyulkyarov, as the use of a memory management unit results in improved performance with regard to memory access, as taught by Zyulkyarov in par. 57.
With respect to claim 7, Narayanan, Ould, and Zyulkyarov teach all limitations of the parent claims. Zyulkyarov further teaches the apparatus according to claim 6, wherein the circuitry is configured to provide access to the persistent memory via a memory mapping technique, with the memory management mapping the persistent memory address space to virtual memory addresses (par. 41 and fig. 4, virtual addresses are mapped to main memory addresses).
With respect to claim 8, Narayanan, Ould, and Zyulkyarov teach all limitations of the parent claims. Zyulkyarov further teaches the apparatus according to claim 7, wherein the circuitry is configured to map the persistent memory to the virtual memory addresses using a pinned page mechanism (pars. 42-43 and fig. 5, mapping using a pin buffer and pinned pages).
With respect to claim 9, Narayanan, Ould, and Zyulkyarov teach all limitations of the parent claims. Zyulkyarov further teaches the apparatus according to claim 7, wherein the circuitry is configured to perform virtual memory registration, by setting up the virtual memory addresses and mapping the virtual memory addresses to addresses of the persistent memory address space (par. 35, the memory configuration operation, which includes mapping virtual addresses to addresses in near memory).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan, Ould and Zyulkyarov as applied to claims 1, 6 and 7 above, and further in view of Beale et al., US PGPub 2011/0154334, hereafter “Beale.”
With respect to claim 10, Narayanan, Ould, and Zyulkyarov teach all limitations of the parent claims, but fail to teach wherein the circuitry is configured to initialize a portion of the persistent memory address space with an alignment of memory addresses that matches the offloading circuitry access alignment requirements. Beale further teaches the apparatus according to claim 7, wherein the circuitry is configured to initialize a portion of the persistent memory address space with an alignment of memory addresses that matches the offloading circuitry access alignment requirements (par. 45, the buffer valid data control work word is aligned with the buffer length control block word multiplied by the number of bytes per word to ensure that the data referenced does not overflow the size of the allocated memory).
It would have been obvious to one of ordinary skill in the art, having the teachings of Narayanan, Ould, Zyulkyarov, and Beale before him before the earliest effective filing date, to modify the memory access system of Narayanan, Ould and Zyulkyarov with the memory access method of Beale, as the offloading method of Beale allows for relatively easy relocation and performance of processing tasks from the first computing environment to the second computing environment, with less complexity and less need for specialized knowledge, as taught by Beale in par. 25.
With respect to claim 11, Narayanan, Ould, Zyulkyarov, and Beale teach all limitations of the parent claims. Beale further teaches the apparatus according to claim 10, wherein alignment of memory addresses is based on multiples of the corresponding memory page sizes (par. 45, the buffer valid data control work word is aligned with the buffer length control block word multiplied by the number of bytes per word to ensure that the data referenced does not overflow the size of the allocated memory. The number of bytes in a word corresponds to the memory page size of the claim).
Response to Arguments
Applicant's arguments filed 11/27/2025 have been fully considered but they are not persuasive. Applicant’s arguments on pages 6-9, with respect to independent claims 1, 18 and 20 are directed towards Beale failing to teach the limitations of the amended claims. These arguments are moot, as Beale is no longer being relied upon for these claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132