Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/30/24, 10/21/24, 11/20/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-9, 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nascetti (International Journal of Circuit Theory and Applications: Vol. 40, no 2, 6/10/22).
With regard to claim 1:Nascetti discloses:
A readout-circuit (figure 2) configured for converting an analog sensor charge
(incoming charge through the input current) into a digital output count (sig-
nal at the output of the counter), wherein the readout-circuit comprises at
least one integrate-and-fire, IAF, circuit (circuit of figure 2 comprising the am-
plifier, the comparator, Cint and the reset switch that correspond exactly
to figure 1 of the current application that is described to be an "IAF" cir-
cuit ), wherein the IAF-circuit is configured for converting the analog sensor
charge into a first digital output count (Integer part), wherein the readout-circuit
is further configured for processing an analog voltage remainder (voltage at '+'
node of the comparator) after a final IAF cycle (the third bullet point
at page 178 : "A/D conversion of the last incomplete charge packet chang-
ing the conversion resolution according to the number of free cells in the
output register"), wherein the readout-circuit comprises at least one analog-to-
digital-converter,A (122), wherein the ADC (ADC of figure 2) is configured
for converting the analog voltage remainder (figure 1, the voltage re-
minder being the amplitude of the last incomplete cycle of the sawtooth
waveform illustrated) into a second digital output (output of the ADC).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-3, 10, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nascetti in view of Landolt (US 2002/0030150).
With regard to claim 2 Nascetti fails to disclose:
The readout-circuit according to claim 1 wherein the readout-circuit is configured for readout of a small analog sensor charge.
Landolt discloses:
The pulse train, in combination with the trajectory of the scanning device can be used to identify the spatial features present in the small image area scanned by this pixel. The image feature is smaller than what would normally be detectable via the specified pixel spacing of the sensor.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to use the teaching of Landolt in the readout circuit of Nascetti for the benefit to generate a complete representation of the analog pixel readout circuit thereby increasing the accuracy and enhancing the clarity of the readout circuit.
With regard to claim 3, Nascetti fails to teach:
The readout circuit according to claim 1 wherein the readout circuit is configured for readout of at least one sensor configured for generating the analog sensor charge dependent on illumination of a light sensitive region of the sensor.
It is well known in the art that sensors are electronic circuits that are configured to collect electrical charges, to capture light intensities to enhance image quality.
With regard to claim 4 Nascetti discloses:
Nascetti discloses in Figure 1 a final uncompleted integration cycle and section 2 (first five lines): The binary fractional representation of the input current is given by the combination of the integer counts and the fraction of the last incomplete charge packet.
With regard to claim 5, Nascetti discloses:
5.The readout-circuit according to claim 1 wherein he IAF circuit comprises at least integrating the output of the operational amplifier between the reference voltage Vref and a comparator voltage Vomp for determining an integration voltage Vint; at least one comparator configured for determining a saturation event, at least one counter configured for determining the first digital output count by counting the saturation events; and at least one mixed signal circuit configured for resetting Vint to Vref after each saturation event ( Fig. 2) .
With regard to claim 6, Nascetti discloses:
6.The readout-circuit according to claim 5 wherein the analog voltage remainder is a leftover voltage after a final IAF cycle that has not triggered a saturation event (Fig. 2).
With regard to claim 7, Nascetti discloses:
7.The readout-circuit according to claim 1 the ADC comprises a counter (Fig. 2//integer part).
With regard to claim 8, Nascetti discloses:
The readout-circuit according to claim 1 the counter type ADC and IAF circuit share an amplifier (Fig. 2).
With regard to claim 9, Nascetti fails to teach:
A photodetector comprising - at least one sensor configured for generating an analog sensor charge dependent on an illumination of a light-sensitive region of the sensor; and- at least one readout-circuit according to claim 1.
Landolt discloses:
An integrate and fire read out circuits (322, 324) composed of photodetector that comprises image sensors (Fig. 7).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teachings of for the benefit to enhance the clarity of the readout circuit.
With regard to claim 10, Nascetti and Landolt fail to teach:
10, The photodetector according to claim 9 wherein the light sensitive region comprises a t least one photoconductive material selected from the group consisting of lead sulfide (PbS); lead selenide (PbSe); mercury cadmium telluride (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimonide (InSb);
indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); Silicon Germanium(SiGe); extrinsic semiconductors.
The above materials are widely used in photodetectors due to their well-established fabrication processes and they either possess good optical properties, effective for visible light detection, efficient in high speed applications, high electron mobility to name a few and to use either one in the fabrication of photo detectors is a matter of design choice or the combination or selection of the integrated electronic circuits the photodetectors are to be used.
With regard to claim 11, Nascetti discloses:
11. A method for readout of an analog sensor charge, the method comprising providing at least one readout-circuit according to claim 1 converting the analog sensor charge into a first digital output count (counter Fig. 2) and analog voltage remainder using the IAF circuit and converting the analog voltage remainder into a second digital output count by using the ADC (fractional part Fig. 2).
With regard to claim 12, Nascetti does not explicitly teach:
12. The method according to the preceding claim 11, further comprising: determining a combined digital output count by combining the first digital output count and the second digital output.
However, it is well known that the final representation of the analog input signal is the sum of the fractional part and the integral part of the signal as disclosed by Nascetti.
With regard to claim 13, Nascetti discloses:
13. A non-transient computer-readable medium including instructions that, when executed by one or more processors, cause the one or more processors to perform the method according to a method claim 11. It is well known in the art that integrated circuits are usually implemented and embedded with computer readable medium that can store and process data in a format that is easily readable, processed and manipulated by computers.
With regard to claim 14, Nascetti and Landolt fail to teach:
14. A method of using the readout- circuit according to claim 1, the method comprising using the readout-circuit for readout of one or more of at least one PbS sensor, at least one PbSe sensor, or at least one pixelated sensor array comprising a plurality of pixels, wherein each of the pixels comprises at least one PbS or PbSe sensor. It is known in the art that all the above materials do have good, can be used in the fabrication of photodetectors are a matter of choice or the readout circuit is to be used.
The above material are widely uses in photodetectors due to their well-
established fabrication processes and they either possess good optical
properties, effective for visible light detection, efficient in high speed
applications, high electron mobility to name a few and to use either one in the in
fabrication of photo detectors is a matter of design choice or the combination or
selection of the integrated electronic circuits the photodetectors are to be used.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845