DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to RCE filed 22 April 2026.
Claims 1 – 2, 4 – 6, 8 – 9, 14 and 16 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 April 2026 has been entered.
Claim Objections
Claims 1 – 2, 4 – 6, 8 – 9, 14 and 16 are objected to because of the following informalities. Appropriate correction is required.
Claim 1 should be amended to “the computer system comprising a central processing unit (CPU), the CPU comprising a plurality of CPU cores and an input/output memory management unit (IOMMU)”. This is so that i) “the CPU core” would not be unclear as to whether it is referring to the one here or the one in which address probing message is being broadcasted to, and ii) “different CPU cores” would be part of the same (and not different) CPU (see spec Fig. 1, 2 and corresponding paragraphs) in which address response message is sent. There is no support for a core of one CPU sending address response message and cores of other CPU deduplicating duplicate of response messages with physical address of another CPU.
Claim 1 should be amended to “determining that no physical address corresponding to the virtual address is found, broadcasting, by the IOMMU, an address probing message to each of the plurality of CPU cores, the address probing message carrying the virtual address”. This is to maintain proper antecedence to amendment supra. In addition, “each CPU core” should correspond to plurality of cores, and not just one core as it would be redundant to have “each CPU core” when there is only one core.
Claim 1 should be amended to “searching, by [[the]] a CPU core of the plurality of CPU cores, for the physical address corresponding to the virtual address in its TLB in response to the address probing message, and sending an address response message to the IOMMU after finding the physical address corresponding to the virtual address, the address response message carrying the found physical address”. This is to maintain consistency to amendments supra. There is no antecedence for “the CPU core”. Also, it is not clear which CPU core, out of each CPU core, is being referred to.
Claim 1 should be amended to “searching, by the CPU core in the found mapping relationship, [[for]] i) the physical address corresponding to the virtual address and ii) the access permission see spec ¶[122]). In addition, Applicant should avoid reciting this limitation as intended use (via use of “for”) because intended use merely recites an context in which the limitation is to operate but does not limit the limitation.
Claim 1 should be amended to “after receiving [[the]] address response messages sent back by different CPU cores, deduplicating the address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU”. There is no antecedence for plural address response messages as only one CPU core is returning address response message. In addition, address response messages, being deduplicated, should be same (and not different) as the ones being received (see spec ¶[122]).
Claim 2 should be amended to “determining that no address response message is received, and in response to determining that no address response message is received, searching, by the IOMMU, for the physical address corresponding to the virtual address based on a process page table in a memory”. This is to avoid reciting this limitation in a contingent manner. For a method claim, a step is not performed if its condition is not met (see MPEP 2111.04(II)). Note that use of “in response to” would not be sufficient because “in response to” merely recites a step to be taken as a result of a condition but is silent as to said condition occurring. In this instance, search in page table is not performed because “no address response message is received” is not recited as occurring. In the interest of compact prosecution, prior art is applied to this limitation (see rejection below). However, said prior art is not necessary because this limitation is not performed.
Claim 5 should be amended to “the computer system comprising a central processing unit (CPU), the CPU comprising a plurality of CPU cores and an input/output memory management unit (IOMMU)”. This is the same issue as claim 1.
Claim 5 should be amended to “in response to determining that the physical address is not found, broadcasting an address probing message to each of the plurality of CPU cores, the address probing message carrying the virtual address”. This is the same issue as claim 1.
Claim 5 should be amended to “wherein [[the]] a CPU core of the plurality of CPU cores searches in its TLB for the physical address corresponding to the virtual address”. This is the same issue as claim 1.
Claim 5 should be amended to “the CPU core searches, in the found mapping relationship, [[for]] i) the physical address corresponding to the virtual address and ii) the access permission
Claim 5 should be amended to “after receiving [[the]] address response messages sent back by different CPU cores, deduplicating the address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU”. This is the same issue as claim 1.
Claim 9 is the IOMMU claim corresponding to method claim 5 and is objected on the same grounds as claim 5.
Claim 6 should be amended to “determining that no address response message is received, and in response to determining that no address response message is received, searching for the physical address corresponding to the virtual address based on a process page table in a memory”.
Claims, dependent upon above identified claims, are also objected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal (US 20190095343) in view of Barrow-Williams (US 20140122829), Ableidinger (US 20110016289), Hayenga (US 20190102388) and Deshpande (US 20160224468).
Regarding claim 1, Gopal teaches
A memory access method applied to a computer system, the computer system comprising a central processing unit (CPU) (CPU = Fig. 7b processor 202), the CPU comprising a CPU core (CPU core = Fig. 7b plural cores 106) and an input/output memory management unit (IOMMU) (IOMMU = Fig. 7b IOMMU/IOTLB 308), the method comprising: (claim objection: This limitation should read “the CPU comprising a plurality of CPU cores and an input/output memory management unit”.)
receiving, by the IOMMU, a memory access request sent by a peripheral component interconnect (PCI) device, the memory access request carrying a virtual address;
searching, by the IOMMU, for a physical address corresponding to the virtual address in its input/output translation look-aside buffer (IOTLB); (Gopal teaches upon memory controller 334 lookup of device TLB that results in a miss, IOMMU (IOMMU)/IOTLB performs snooping (see Fig. 7b, ¶[88]) by sending (receiving) request (memory access request) to said IOMMU that uses VA (virtual address) to check (searching) said IOTLB (IOTLB) (in (its) said IOMMU (see ¶[64])) for PA (physical address) (see ¶[85]). Gopal also teaches said memory controller 334 is in accelerator 332 (PCI device) (see Fig. 7b) that is connected to PCIe (PCI) (see ¶[41]), and ii) said request includes said VA (see ¶[243]).)
determining that no physical address corresponding to the virtual address is found, broadcasting, by the IOMMU, an address probing message to each CPU core, the address probing message carrying the virtual address; (claim objection: This limitation should read “an address probing message to each of the plurality of CPU cores”.)
searching, by the CPU core, for the physical address corresponding to the virtual address in its TLB in response to the address probing message, and sending an address response message to the IOMMU after finding the physical address corresponding to the virtual address, the address response message carrying the found physical address; and (claim objection: This limitation should read “searching, by a CPU of the plurality of CPU cores, for the physical address corresponding to the virtual address in its TLB in response to the address probing message”.) (Gopal teaches when said IOTLB is a miss (not found) for said PA (physical address) checked using said virtual address (virtual address), said IOMMU/IOTLB sends snoop TLBs (address probing message) using said virtual address 706 (address) to CPU core TLBs (see Fig. 7b, ¶[85], [88]) wherein said snoop TLBs using said virtual address 706 is broadcast (broadcast) to all cores (each CPU core) (see Fig. 7b, ¶[26]). Note that said snoop TLBs using said virtual address 706 already includes (carrying) said virtual address. Gopal further teaches said virtual address (from (in response to) said snoop TLBs using said virtual address 706) is used to lookup (searching) said CPU core TLBs (see Fig. 7b, ¶[85]) for said physical address (physical address) (see ¶[58]). Gopal also teaches that said CPU core TLBs is representative of all TLBs of each of said cores (see Fig. 2, ¶[33-34],[46]) wherein each of said core (each CPU core) is responsible to search its respective TLB (TLB) (see ¶[126]).)
receiving, by the IOMMU, the address response message sent by the CPU core, storing a mapping relationship between the physical address and the virtual address in its IOTLB, and performing memory access based on the physical address (Gopal teaches when said snoop TLBs using said virtual address 706 (address probing message) search results in a hit in said CPU core TLBs for said virtual address, copying (receive), from (sent) said CPU core TLBs of each of said core (each CPU core), TLB entry (address response message) (said VA (virtual address)- said PA (physical address) translation (mapping relationship)) to (store) said IOMMU/IOTLB (IOTLB) wherein said VA-said PA translation is used to (based on) access (memory access) memory 310 (see Fig. 7b, ¶[85]).)
As noted in claim 1, Gopal teaches sending snoop TLBs (address probing message) using virtual address (address) where each core (each CPU core) is responsible to search its respective TLB (TLB) for physical address (physical address) using said virtual address but does not appear to explicitly teach using address space identifier (ASID) to search for said physical address in the following manner.
wherein the address probing message further carries an address space identifier [and an access permission], wherein the address space identifier is bound to a process identifier of an application program to achieve address isolation between applications, and searching, by the CPU core, for the physical address corresponding to the virtual address in its TLB comprises:
searching, by the CPU core, for a mapping relationship, that matches the address space identifier, between the virtual address and the physical address, in its TLB: and
searching, by the CPU core, for the physical address corresponding to the virtual address [and the access permission] in the found mapping relationship
However, Barrow-Williams teaches
wherein the address probing message further carries an address space identifier [and an access permission], wherein the address space identifier is bound to [a process identifier of] an application program to achieve address isolation between applications, and searching, by [the] CPU core, for the physical address corresponding to the virtual address in its TLB comprises: (Barrow-William teaches assigning (bound) address space identifier (ASID) (address space identifier) each of multiple tasks (application program, applications) having an independent (isolation) virtual address space (see Barrow-Williams abstract, ¶[10]).)
searching, by the CPU core, for a mapping relationship, that matches the address space identifier, between the virtual address and the physical address, in its TLB: and
searching, by the CPU core, for the physical address corresponding to the virtual address [and the access permission] in the found mapping relationship (claim objection: This limitation should read “searching, by the CPU core in the found mapping relationship, i) the physical address corresponding to the virtual address and ii) the access permission”.) (Barrow-Williams a TLB hit occurs when TLB (its TLB) (in PPU (CPU core) (see Fig. 4A)) includes a cache entry (mapping relationship) that matches (matches) both ASID (address space identifier) and virtual address (virtual address) inputs (carry) for a memory access request (address probing message) wherein when said TLB hit occurs, corresponding (corresponding) physical address (physical address) is provided (searching) (see ¶[76]). Barrow-Williams also teaches i) said ASID and said virtual address being stored as a pair for search tag (searching) for said TLB hit (see ¶[76]), ii) said cache entry maps said virtual address to (between) said physical address (see Fig. 4D) and iii) MMU (in PPU (CPU core)) performing translation functions (see ¶[53]).)
In view of Barrow-Williams, Gopal is modified such that said physical address is searched, by said CPU core, by identifying, in its TLB, a cache entry (mapping relationship) that matched ASID (address space identifier) and said virtual address (virtual address) wherein said ASID is assigned (bound) to each one of tasks (application program, applications) having independent (isolation) virtual address space.
Gopal and Barrow-Williams are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Gopal in the manner described supra because use of ASID allows for simultaneous execution of different task having different virtual address space, thus improving performance of applications (Barrow-Williams, ¶[7-10]). In addition, execution of tasks with address space isolation also improves reliability (see Barrow-Williams, ¶[7-10]).
As noted in claim 1, modified Gopal teaches a base method where address space identifier is bound to application program. The claimed invention improves upon said base method by binding said address space identifier in the following manner.
wherein the address space identifier is bound to a process identifier of an application program
This improvement to said base method is an application of known technique from Ableindinger – mapping ASID to PID of application process. In particular, Ableidinger teaches
wherein the address space identifier is bound to a process identifier of an application program (Ableidinger teaches ASID is mapped (bound) to PID (process identifier) (see Fig. 6, ¶[30]) wherein said PID is associated with process of an application (application program) (see Fig. 3, ¶[25]).)
One of ordinary skill in the art would recognize that this known technique of using a PID to link ASID to application process can also be applied to modified Gopal’s ASID bound to application program, and the result would have been predictable. In this instance, modified Gopal’s ASID would be linked to PID that is associated with said application program. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Albleindinger’s known technique would have yielded i) predictable result of said ASID (address space identifier) being linked to PID (process identifier) that is associated with said application program, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
As noted in claim 1, modified Gopal teaches a base method of finding, in a TLB, a mapping relationship that matches address space identifier in address probing message. The claimed invention improves upon said base method by also searching, in said mapping relationship, access permission found in said address probing message (see also limitation below).
wherein the address probing message further carries an address space identifier and an access permission
searching, by the CPU core, for the physical address corresponding to the virtual address and the access permission in the found mapping relationship
This improvement to said base method is an application of known technique from Hayenga – checking (searching) whether additional parameters (access permission), provided with address translation request (address probing message), satisfy access permissions (access permission) in matching (found) TLB entry (found mapping relationship) (see Hayenga ¶[61]) that store data for translating virtual address to corresponding physical address (see Hayenga ¶[63]).
One of ordinary skill in the art would recognize that this known technique of checking in TLB entry for access permission of address translation request can also be applied to search modified Gopal’s mapping relationship found in TLB, and the result would have been predictable. In this instance, said mapping relationship is searched for access permission that is included in said address probing message. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Hayenga’s known technique would have yielded i) predictable result of said mapping relationship being searched for access permission that is included in said address probing message, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
As noted in claim 1, modified Gopal teaches CPU core sending, to IOMMU, address response message carrying physical address but does not appear to explicitly teach deduplicating said address response message that carry the same search result (see also limitation below).
wherein the method further comprises:
after receiving the address response messages sent back by different CPU cores, deduplicating address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU
However, Deshpande teaches
wherein the method further comprises:
after receiving the address response messages sent back by different CPU cores, deduplicating address response messages carrying a same search result, to only send back one address response message [carrying the physical address to the IOMMU] (claim objection: This limitation should read “after receiving address response messages sent back by different CPU cores of the plurality of CPU cores, deduplicating the address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU”.) (Deshpande teaches tracking coherency responses, from neighboring nodes (different CPU cores) each with core processor (CPU cores) (see Fig. 2, ¶[26]), and (after) incorporate (deduplicating) said received (after) coherency responses (responsive to same (same) outstanding snoop request) into a single combined coherency response (one address response message) that is forwarded (only send back one address response message) (see ¶[28]) wherein said coherency responses, each, include information about requested data (search result) in response to said same (same) outstanding snoop request (see Fig. 3, ¶[30]). Note that incorporating, into said single combined coherency response, said received coherency responses (each with said requested data to said same outstanding snoop request) reduces (deduplicating) the amount of said coherency responses with the same requested data.)
In view of Deshpande, modified Gopal is further modified such that said address response message (carrying said found physical address (search result), and is sent to IOMMU), when received from different CPU cores, is incorporated (deduplicating) into a single coherency response message (one address response message) wherein said address response message is responsive to said same (same) address probing message.
Gopal, Barrow-Williams, Ableidinger, Hayenga and Deshpande are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to further modify modified Gopal in the manner described supra because it would results in fewer coherence responses being transmitted, reducing congestion and improving scalability of snooping coherency protocols (Deshpande ¶[19-20]).
Regarding claim 5, Gopal teaches
A memory access method for memory access of a computer system, the computer system comprising a central processing unit (CPU), the CPU comprising a CPU core and an input/output memory management unit (IOMMU), the method being applied to the IOMMU, comprising:
receiving a memory access request sent by a peripheral component interconnect (PCI) device, the memory access request carrying a virtual address;
searching for a physical address corresponding to the virtual address in an input/output translation look-aside buffer (IOTLB); (Gopal teaches the above limitations (see above claim 1 mapping).)
in response to determining that the physical address is not found, and broadcasting an address probing message to each CPU core, the address probing message carrying the virtual address, wherein the CPU core searches in its TLB for the physical address corresponding to the virtual address; (These mappings are provided in the interest of compact prosecution but are not required due to recitation of contingent limitations. For a method claim, a limitation is not performed if the condition(s) for said limitation is not met (see MPEP 2111.04(II)). In this instance, “in response to” merely recites a step to be taken as a result of a condition but is silent as to said condition occurring/met. As such, broadcasting and searching steps are not performed because not finding physical address is not positively recited as occurring.) (Gopal teaches when said IOTLB is a miss (not found) for said PA (physical address) checked using said virtual address (virtual address), said IOMMU/IOTLB sends snoop TLBs using said virtual address 706 (address probing message) to CPU core TLBs (see Fig. 7b) wherein said snoop TLBs using said virtual address 706 is broadcast (broadcast) to all cores (each CPU core) (see Fig. 7b, ¶[26]). Note that said snoop TLBs using said virtual address 706 already includes (carrying) said virtual address. Gopal further teaches that said snoop TLBs using said virtual address 706 uses said virtual address to search said CPU core TLBs (see Fig. 7b, ¶[85]) for said physical address (physical address) (see ¶[58]). Gopal also teaches that said CPU core TLBs is representative of all TLBs of each of said cores (see Fig. 2, ¶[33-34],[46]) wherein each of said core (each CPU core) is responsible to search its respective TLB (TLB) (see ¶[126]).)
receiving an address response message sent by the CPU core in response to the address probing message, the address response message carrying the physical address corresponding to the virtual address found by the CPU core; and
storing the mapping relationship between the physical address and the virtual address in the IOTLB and performing memory access based on the physical address (These mappings are provided in the interest of compact prosecution but are not required due to recitation of contingent limitations. As previously noted, due to contingent limitation, step of broadcasting address probing message does not occur. As such, steps that depends on (or triggered by) this address probing message also does not occur.) (Gopal teaches when said snoop TLBs using said virtual address 706 (address probing message) search results in a hit in said CPU core TLBs for said virtual address, copying (receive), from (sent) said CPU core TLBs of each of said core (each CPU core), TLB entry (address response message) (said VA (virtual address)- said PA (physical address) translation (mapping relationship)) to (store) said IOMMU/IOTLB (IOTLB) wherein said VA-said PA translation is used to (based on) access (memory access) memory 310 (see Fig. 7b, ¶[85]).)
As noted in claim 5, Gopal teaches sending snoop TLBs (address probing message) using virtual address (address) where each core (each CPU core) is responsible to search its respective TLB (TLB) for physical address (physical address) using said virtual address but does not appear to explicitly teach using address space identifier (ASID) to search for said physical address in the following manner.
wherein the address probing message further carries an address space identifier [and an access permission], wherein the address space identifier is bound to a process identifier of an application program to achieve address isolation between applications,
wherein the CPU core searches in its TLB for a mapping relationship, that matches the address space identifier, between the virtual address and the physical address, and the CPU core search for the physical address corresponding to the virtual address [and the access permission] in the found mapping relationship
However, Barrow-Williams teaches
wherein the address probing message further carries an address space identifier [and an access permission], wherein the address space identifier is bound to [a process identifier of] an application program to achieve address isolation between applications, (Barrow-William teaches assigning (bound) address space identifier (ASID) (address space identifier) each of multiple tasks (application program, applications) having an independent (isolation) virtual address space (see Barrow-Williams abstract, ¶[10]).)
wherein the CPU core searches in its TLB for a mapping relationship, that matches the address space identifier, between [the] a virtual address and the physical address, and the CPU core search for the physical address corresponding to the virtual address in the found mapping relationship (claim objection: This limitation should read “the CPU core searches, in the found mapping relationship, i) the physical address corresponding to the virtual address and ii) the access permission”.) (Barrow-Williams a TLB hit occurs when TLB (its TLB) (in PPU (CPU core) (see Fig. 4A)) includes a cache entry (mapping relationship) that matches (matches) both ASID (address space identifier) and virtual address (virtual address) inputs (carry) for a memory access request (address probing message) wherein when said TLB hit occurs, corresponding (corresponding) physical address (physical address) is provided (searching) (see ¶[76]). Barrow-Williams also teaches i) said ASID and said virtual address being stored as a pair for search tag (searching) for said TLB hit (see ¶[76]), ii) said cache entry maps said virtual address to (between) said physical address (see Fig. 4D) and iii) MMU (in PPU (CPU core)) performing translation functions (see ¶[53]).)
In view of Barrow-Williams, Gopal is modified such that said physical address is searched, by said CPU core, by identifying, in its TLB, a cache entry (mapping relationship) that matched ASID (address space identifier) and said virtual address (virtual address) wherein said ASID is assigned (bound) to each one of tasks (application program, applications) having independent (isolation) virtual address space.
Gopal and Barrow-Williams are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Gopal in the manner described supra because use of ASID allows for simultaneous execution of different task having different virtual address space, thus improving performance of applications (Barrow-Williams, ¶[7-10]). In addition, execution of tasks with address space isolation also improves reliability (see Barrow-Williams, ¶[7-10]).
As noted in claim 5, modified Gopal teaches a base method where address space identifier is bound to application program. The claimed invention improves upon said base method by binding said address space identifier in the following manner.
wherein the address space identifier is bound to a process identifier of an application program
This improvement to said base method is an application of known technique from Ableindinger – mapping ASID to PID of application process. In particular, Ableidinger teaches
wherein the address space identifier is bound to a process identifier of an application program (Ableidinger teaches ASID is mapped (bound) to PID (process identifier) (see Fig. 6, ¶[30]) wherein said PID is associated with process of an application (application program) (see Fig. 3, ¶[25]).)
One of ordinary skill in the art would recognize that this known technique of using a PID to link ASID to application process can also be applied to modified Gopal’s ASID bound to application program, and the result would have been predictable. In this instance, modified Gopal’s ASID would be linked to PID that is associated with said application program. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Albleindinger’s known technique would have yielded i) predictable result of said ASID (address space identifier) being linked to PID (process identifier) that is associated with said application program, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
As noted in claim 5, modified Gopal teaches a base method of finding, in a TLB, a mapping relationship that matches address space identifier in address probing message. The claimed invention improves upon said base method by also searching, in said mapping relationship, access permission found in said address probing message (see also limitation below).
wherein the address probing message further carries an address space identifier and an access permission
the CPU core searches for the physical address corresponding to the virtual address and the access permission in the found mapping relationship
This improvement to said base method is an application of known technique from Hayenga – checking (searching) whether additional parameters (access permission), provided with address translation request (address probing message), satisfy access permissions (access permission) in matching (found) TLB entry (found mapping relationship) (see Hayenga ¶[61]) that store data for translating virtual address to corresponding physical address (see Hayenga ¶[63]).
One of ordinary skill in the art would recognize that this known technique of checking in TLB entry for access permission of address translation request can also be applied to search modified Gopal’s mapping relationship found in TLB, and the result would have been predictable. In this instance, said mapping relationship is searched for access permission that is included in said address probing message. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Hayenga’s known technique would have yielded i) predictable result of said mapping relationship being searched for access permission that is included in said address probing message, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
As noted in claim 5, modified Gopal teaches CPU core sending, to IOMMU, address response message carrying physical address but does not appear to explicitly teach deduplicating said address response message that carry the same search result (see also limitation below).
wherein the method further comprises:
after receiving the address response messages sent back by different CPU cores, deduplicating address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU
However, Deshpande teaches
wherein the method further comprises:
after receiving the address response messages sent back by different CPU cores, deduplicating address response messages carrying a same search result, to only send back one address response message [carrying the physical address to the IOMMU] (claim objection: This limitation should read “after receiving address response messages sent back by different CPU cores of the plurality of CPU cores, deduplicating the address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU”.) (Deshpande teaches tracking coherency responses, from neighboring nodes (different CPU cores) each with core processor (CPU cores) (see Fig. 2, ¶[26]), and (after) incorporate (deduplicating) said received coherency responses (responsive to same (same) outstanding snoop request) into a single combined coherency response (one address response message) that is forwarded (only send back one address response message) (see ¶[28]) wherein said coherency responses, each, include information about requested data (search result) in response to said same (same) outstanding snoop request (see Fig. 3, ¶[30]). Note that incorporating, into said single combined coherency response, said received coherency responses (each with said requested data to said same outstanding snoop request) reduces (deduplicating) the amount of said coherency responses with the same requested data.)
In view of Deshpande, modified Gopal is further modified such that said address response message (carrying said found physical address (search result), and is sent to IOMMU), when received from different CPU cores, is incorporated (deduplicating) into a single coherency response message (one address response message) wherein said address response message is responsive to said same (same) address probing message.
Gopal, Barrow-Williams, Ableidinger, Hayenga and Deshpande are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to further modify modified Gopal in the manner described supra because it would results in fewer coherence responses being transmitted, reducing congestion and improving scalability of snooping coherency protocols (Deshpande ¶[19-20]).
Regarding claim 9, Gopal teaches
An input-output memory management unit (IOMMU) (IOMMU = Fig. 7b IOMMU/IOTLB 308) configured to:
receive a memory access request sent by a peripheral component interconnect (PCI) device, the memory access request carrying a virtual address;
search for a physical address corresponding to the virtual address in an input/output translation look-aside buffer (IOTLB); (Gopal teaches upon memory controller 334 lookup of device TLB that results in a miss, IOMMU (IOMMU)/IOTLB performs snooping (see Fig. 7b, ¶[88]) by sending (receiving) request (memory access request) to said IOMMU that uses VA (virtual address) to check (searching) said IOTLB (IOTLB) (in (its) said IOMMU (see ¶[64])) for PA (physical address) (see ¶[85]). Gopal also teaches i) said memory controller 334 is in accelerator 332 (PCI device) (see Fig. 7b) that is connected to PCIe (PCI) (see ¶[41]), and ii) said request includes said VA (see ¶[243]).)
in response to determining that the physical address is not found, broadcast an address probing message to each CPU core, the address probing message carrying the virtual address, wherein the CPU core searches in its TLB for the physical address corresponding to the virtual address; (Gopal teaches when said IOTLB is a miss (not found) for said PA (physical address) checked using said virtual address (virtual address), said IOMMU/IOTLB sends snoop TLBs using said virtual address 706 (address probing message) to CPU core TLBs (see Fig. 7b) wherein said snoop TLBs using said virtual address 706 is broadcast (broadcast) to all cores (each CPU core) (see Fig. 7b, ¶[26]). Note that said snoop TLBs using said virtual address 706 already includes (carrying) said virtual address. Gopal further teaches that said snoop TLBs using said virtual address 706 uses said virtual address to search said CPU core TLBs (see Fig. 7b, ¶[85]) for said physical address (physical address) (see ¶[58]). Gopal also teaches that said CPU core TLBs is representative of all TLBs of each of said cores (see Fig. 2, ¶[33-34],[46]) wherein each of said core (each CPU core) is responsible to search its respective TLB (TLB) (see ¶[126]).)
receive an address response message sent by the CPU core in response to the address probing message, wherein the address response message carries the physical address corresponding to the virtual address found by the CPU core; and
store a mapping relationship between the physical address and the virtual address in the IOTLB and perform memory access based on the physical address (Gopal teaches when said snoop TLBs using said virtual address 706 (address probing message) search results in a hit in said CPU core TLBs for said virtual address, copying (receive), from (sent) said CPU core TLBs of each of said core (each CPU core), TLB entry (address response message) (said VA (virtual address)- said PA (physical address) translation (mapping relationship)) to (store) said IOMMU/IOTLB (IOTLB) wherein said VA-said PA translation is used to (based on) access (memory access) memory 310 (see Fig. 7b, ¶[85]).)
As noted in claim 9, Gopal teaches sending snoop TLBs (address probing message) using virtual address (address) where each core (each CPU core) is responsible to search its respective TLB (TLB) for physical address (physical address) using said virtual address but does not appear to explicitly teach using address space identifier (ASID) to search for said physical address in the following manner.
wherein the address probing message further carries an address space identifier [and an access permission], wherein the address space identifier is bound to a process identifier of an application program to achieve address isolation between applications, and the CPU core searches in its TLB for the physical address corresponding to the virtual address comprises:
searching, by the CPU core, for a mapping relationship, that matches the address space identifier, between the virtual address and the physical address, in its TLB: and
searching, by the CPU core, for the physical address corresponding to the virtual address [and the access permission] in the found mapping relationship
However, Barrow-Williams teaches
wherein the address probing message further carries an address space identifier [and an access permission], wherein the address space identifier is bound to [a process identifier of] an application program to achieve address isolation between applications, and [the] CPU core searching in its TLB for the physical address corresponding to the virtual address comprises: (Barrow-William teaches assigning (bound) address space identifier (ASID) (address space identifier) each of multiple tasks (application program, applications) having an independent (isolation) virtual address space (see Barrow-Williams abstract, ¶[10]).)
searching, by the CPU core, for a mapping relationship, that matches the address space identifier, between the virtual address and the physical address, in its TLB: and
searching, by the CPU core, for the physical address corresponding to the virtual address [and the access permission] in the found mapping relationship (Barrow-Williams a TLB hit occurs when TLB (its TLB) (in PPU (CPU core) (see Fig. 4A)) includes a cache entry (mapping relationship) that matches (matches) both ASID (address space identifier) and virtual address (virtual address) inputs (carry) for a memory access request (address probing message) wherein when said TLB hit occurs, corresponding (corresponding) physical address (physical address) is provided (searching) (see ¶[76]). Barrow-Williams also teaches i) said ASID and said virtual address being stored as a pair for search tag (searching) for said TLB hit (see ¶[76]), ii) said cache entry maps said virtual address to (between) said physical address (see Fig. 4D) and iii) MMU (in PPU (CPU core)) performing translation functions (see ¶[53]).)
In view of Barrow-Williams, Gopal is modified such that said physical address is searched, by said CPU core, by identifying, in its TLB, a cache entry (mapping relationship) that matched ASID (address space identifier) and said virtual address (virtual address) wherein said ASID is assigned (bound) to each one of tasks (application program, applications) having independent (isolation) virtual address space.
Gopal and Barrow-Williams are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Gopal in the manner described supra because use of ASID allows for simultaneous execution of different task having different virtual address space, thus improving performance of applications (Barrow-Williams, ¶[7-10]). In addition, execution of tasks with address space isolation also improves reliability (see Barrow-Williams, ¶[7-10]).
As noted in claim 9, modified Gopal teaches a base device where address space identifier is bound to application program. The claimed invention improves upon said base method by binding said address space identifier in the following manner.
wherein the address space identifier is bound to a process identifier of an application program
This improvement to said base device is an application of known technique from Ableindinger – mapping ASID to PID of application process. In particular, Ableidinger teaches
wherein the address space identifier is bound to a process identifier of an application program (Ableidinger teaches ASID is mapped (bound) to PID (process identifier) (see Fig. 6, ¶[30]) wherein said PID is associated with process of an application (application program) (see Fig. 3, ¶[25]).)
One of ordinary skill in the art would recognize that this known technique of using a PID to link ASID to application process can also be used to link to modified Gopal’s ASID bound to application program, and the result would have been predictable. In this instance, modified Gopal’s ASID would be linked to PID that is associated with said application program. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Albleindinger’s known technique would have yielded i) predictable result of said ASID (address space identifier) being linked to PID (process identifier) that is associated with said application program, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
As noted in claim 9, modified Gopal teaches a base method of finding, in a TLB, a mapping relationship that matches address space identifier in address probing message. The claimed invention improves upon said base method by also searching, in said mapping relationship, access permission found in said address probing message (see also limitation below).
wherein the address probing message further carries an address space identifier and an access permission
searching, by the CPU core, for the physical address corresponding to the virtual address and the access permission in the found mapping relationship
This improvement to said base method is an application of known technique from Hayenga – checking (searching) whether additional parameters (access permission), provided with address translation request (address probing message), satisfy access permissions (access permission) in matching (found) TLB entry (found mapping relationship) (see Hayenga ¶[61]) that store data for translating virtual address to corresponding physical address (see Hayenga ¶[63]).
One of ordinary skill in the art would recognize that this known technique of checking in TLB entry for access permission of address translation request can also be applied to search modified Gopal’s mapping relationship found in TLB, and the result would have been predictable. In this instance, said mapping relationship is searched for access permission that is included in said address probing message. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Hayenga’s known technique would have yielded i) predictable result of said mapping relationship being searched for access permission that is included in said address probing message, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
As noted in claim 9, modified Gopal teaches CPU core sending, to IOMMU, address response message carrying physical address but does not appear to explicitly teach deduplicating said address response message that carry the same search result (see also limitation below).
wherein the method further comprises:
after receiving the address response messages sent back by different CPU cores, deduplicating address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU
However, Deshpande teaches
wherein the method further comprises:
after receiving the address response messages sent back by different CPU cores, deduplicating address response messages carrying a same search result, to only send back one address response message [carrying the physical address to the IOMMU] (claim objection: This limitation should read “after receiving address response messages sent back by different CPU cores of the plurality of CPU cores, deduplicating the address response messages carrying a same search result, to only send back one address response message carrying the physical address to the IOMMU”.) (Deshpande teaches tracking coherency responses, from neighboring nodes (different CPU cores) each with core processor (CPU cores) (see Fig. 2, ¶[26]), and (after) incorporate (deduplicating) said received coherency responses (responsive to same (same) outstanding snoop request) into a single combined coherency response (one address response message) that is forwarded (only send back one address response message) (see ¶[28]) wherein said coherency responses, each, include information about requested data (search result) in response to said same (same) outstanding snoop request (see Fig. 3, ¶[30]). Note that incorporating, into said single combined coherency response, said received coherency responses (each with said requested data to said same outstanding snoop request) reduces (deduplicating) the amount of said coherency responses with the same requested data.)
In view of Deshpande, modified Gopal is further modified such that said address response message (carrying said found physical address (search result), and is sent to IOMMU), when received from different CPU cores, is incorporated (deduplicating) into a single coherency response message (one address response message) wherein said address response message is responsive to said same (same) address probing message.
Gopal, Barrow-Williams, Ableidinger, Hayenga and Deshpande are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to further modify modified Gopal in the manner described supra because it would results in fewer coherence responses being transmitted, reducing congestion and improving scalability of snooping coherency protocols (Deshpande ¶[19-20]).
Claims 2, 6 and 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Barrow-Williams, Ableidinger, Hayenga and Deshpande, and further in view of Ng (US 20220206700).
Regarding claim 2, Gopal in view of Barrrow-Williams, Ableidinger, Hayenga and Deshpande teach the method of claim 1 that searches physical address corresponding to virtual address in TLB but do not appear to explicitly teach
in response to determining that no address response message is received, searching for the physical address corresponding to the virtual address based on a process page table in a memory
However, Ng teaches
in response to determining that no address response message is received, searching for [the] physical address corresponding to [the] virtual address based on a process page table in a memory (Ng teaches in response to entry (mapping virtual address to physical address) not present (no address response message received) in TLB, IOMMU performs page table walk (process) that searches page table (process page table), in memory (memory), for entry that provides said physical address associated with said virtual address wherein said TLB is in CPU (see ¶[19-20]).)
In view of Ng, modified Gopal is modified such that when said search, said TLB, for entry (mapping said virtual address to said physical address) is not present (no address response message received), said IOMMU perform page table walk (process) that search page table (process page table), in memory (memory), for entry that maps said virtual address to said physical address.
Gopal, Barrrow-Williams, Ableidinger, Hayenga, Deshpande and Ng are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modifed Gopal in the manner described supra because it would avoid having software/IO devices keep track of physical locations in memory (see Ng, ¶[18]).
Regarding claim 6, Gopal in view of Barrrow-Williams, Ableidinger, Hayenga and Deshpande teach the method of claim 5 that searches physical address corresponding to virtual address in TLB but does not appear to explicitly teach
in response to determining that no address response message is received, searching for the physical address corresponding to the virtual address based on a process page table in a memory
However, Ng teaches
in response to determining that no address response message is received, searching for [the] physical address corresponding to [the] virtual address based on a process page table in a memory (Ng teaches this limitation (see above claim 2 mapping).)
In view of Ng, modified Gopal is modified such that when said search, said TLB, for entry (mapping said virtual address to said physical address) is not present (no address response message received), said IOMMU perform page table walk (process) that search page table (process page table), in memory (memory), for entry that maps said virtual address to said physical address.
Gopal, Barrrow-Williams, Ableidinger, Hayenga and Deshpande and Ng are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modfified Gopal in the manner described supra because it would avoid having software/IO devices keep track of physical locations in memory (see Ng, ¶[18]).
Claim 14 is the IOMMU claim corresponding to method claim 6, and is rejected on the same grounds as claim 6.
Claims 4, 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gopal in view of Barrow-Williams, Ableidinger, Hayenga and Deshpande, and further in view of Pong (US 6341337).
Regarding claim 4, Gopal in view of Barrrow-Williams, Ableidinger, Hayenga and Deshpande teach the method of claim 1 where address probing message is broadcast to each CPU core but does not appear to explicitly teach said address probing message is as follows.
broadcasting the address probing message to each CPU core based on a cache detection snoop protocol
However, Pong teaches
broadcasting [the] address probing message to each CPU core based on a cache detection snoop protocol (Pong teaches implementing snoop protocol (cache detection snoop protocol) that (based on) broadcast (broadcasting) read miss transaction (address probing message) that causes each node (each CPU core) (includes a processor (see Fig. 3)) to search (detection) its cache (cache) for requested address (address) (see col 3 ln 44-65).)
In view of Pong, modified Gopal is modified such that said address probing message is read miss transaction (part of snoop protocol (cache detection snoop protocol)) that searches cache of each CPU core.
Gopal, Barrrow-Williams, Ableidinger, Hayenga and Deshpande and Pong are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Gopal in the manner described supra because it would reduce bus traffic by only fetching from main memory when other node has no data (see Pong col 8 ln 18-26).
Regarding claim 8, Gopal in view of Barrrow-Williams, Ableidinger, Hayenga and Deshpande teach the method of claim 5 where address probing message is broadcast to each CPU core but does not appear to explicitly teach said address probing message is as follows.
broadcasting the address probing message to each CPU core based on a cache detection snoop protocol
However, Pong teaches
broadcasting [the] address probing message to each CPU core based on a cache detection snoop protocol (Pong teaches this limitation (see above claim 4 mapping).)
In view of Pong, modified Gopal is modified such that said address probing message is read miss transaction (part of snoop protocol (cache detection snoop protocol)) that searches cache of each CPU core.
Gopal, Barrrow-Williams, Ableidinger, Hayenga, Deshpande and Pong are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify modified Gopal in the manner described supra because it would reduce bus traffic by only fetching from main memory when other node has no data (see Pong col 8 ln 18-26).
Claim 16 is the IOMMU claim corresponding to method claim 8, and is rejected on the same grounds as claim 8.
Response to Remarks
Applicant’s remarks, with respect to the rejections of the claims based on newly amended limitations, have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly identified prior art (see rejection supra).
Additional Remarks
In order to address contingent limitations in claim 5, claim 5 should be amended to “determining that the physical address is not found, and in response to determining that the physical address is not found, broadcasting an address probing message to each CPU core, the address probing message carrying the virtual address, wherein the CPU core searches in its TLB for the physical address corresponding to the virtual address”. It is noted that both limitations are required as previous amendments to avoid either limitation resulted in i) claim objection (see Office Action mailed January 2026) and ii) contingent limitations (see supra).
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139
