DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final Office Action Correspondence in response to U.S. Application No. 18/842,930 filed on 08/30/2024.
Claims 1-8 are pending. Claims 1, 6 and 8 are independent claims.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/30/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 1 and 6 are objected to because of the following informalities:
In claim 1, it should include a semicolon (“;”) at the end of “a request-related processing part” and also at the end of “a request I/O part” limitations; and the abbreviated word “I/O” should be spelled out at least once
In claim 6, it should include a semicolon (“;”) at the end of “a request-related processing part” limitation; and the abbreviated word “I/O” should be spelled out at least once
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over THYAGATURU et al. (U.S. PG Pub. No. 2022/0075655 A1, hereinafter “THYAGATURU”) in view of JEAUGEY et al. (U.S. PG Pub. No. 2015/0095920 A1, hereinafter “JEAUGEY”).
Regarding claim 1, THYAGATURU teaches an accelerator offload device that offloads specific processing of an application program to an accelerator, the accelerator offload device comprising:
a request-related processing part (THYAGATURU ¶¶0042-0043)
a request I/O part (THYAGATURU ¶¶0042-0043)
a response I/O part (THYAGATURU ¶¶0042-0043); and
a response-related processing part (THYAGATURU ¶¶0042-0043),
wherein the request-related processing part is configured to perform predetermined processing required before performing offloading to the accelerator and then notify the request I/O part of a request to perform offloading (THYAGATURU ¶0043);
wherein the request I/O part is configured to operate on a first CPU core to perform request processing of notifying the accelerator of an offload request (THYAGATURU Claim 1);
wherein the response I/O part is configured to operate on a second CPU core different from the first CPU core perform response processing of notifying the response-related processing part of operation completion of the accelerator (THYAGATURU Claim 1).
THYAGATURU fails to explicitly teach the response-related processing part is configured to perform an operation described in the application program by using an operation result of the accelerator. However, in the same field of endeavor, JEAUGEY teaches the response-related processing part is configured to perform an operation described in the application program by using an operation result of the accelerator (JEAUGEY ¶¶0052-0053).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify THYAGATURU by incorporating the teachings of JEAUGEY. The motivation would be to provide benefits from more specialized architectures for a given type of task. This specialization and the adequateness of the peripheral unit for the task to be executed ensures gains in performance (JEAUGEY ¶0004).
As to claim 2, THYAGATURU as modified by JEAUGEY also teaches the accelerator offload device according to claim 1, further comprising a management part configured to manage a CPU core group composed of a plurality of CPU cores including the first CPU core and the second CPU core (THYAGATURU Fig. 3a, i.e., multiple cores are utilized),
wherein the management part is configured to determine a CPU core to be used by the request-related processing part, the response-related processing part, the request I/O part, or the response I/O part from among the CPU core group (THYAGATURU Fig. 4).
As to claim 3, THYAGATURU as modified by JEAUGEY also teaches the accelerator offload device according to claim 2, wherein the response I/O part is a functional part dedicated to response processing, and wherein the management part is further configured to exclusively allocate one of the plurality of CPU cores to the response I/O part as the second CPU core (THYAGATURU Fig. 5, steps 508-510).
As to claim 4, THYAGATURU as modified by JEAUGEY also teaches the accelerator offload device according to claim 1, further comprising a task scheduler configured to, when a task that needs to be offloaded to the accelerator occurs, register the task in a task queue of the request-related processing part (THYAGATURU ¶0033, i.e., OS task scheduling),
wherein the task scheduler registers the task as a task using a third CPU core different from the second CPU core used by the response I/O part (THYAGATURU Fig. 2a).
Claim 6 recites the limitations substantially similar to those of claim 1 and is similarly rejected.
Claim 8 recites the limitations substantially similar to those of claim 1 and is similarly rejected.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over THYAGATURU in view of JEAUGEY, and further in view of EOM et (U.S. PG Pub. No. 2021/0303057 A1, hereinafter “EOM”).
As to claim 5, THYAGATURU as modified by JEAUGEY teaches the accelerator offload device according to claim 4, but fails to explicitly teach wherein the task scheduler comprises a sleep control part configured to, when there is no task to be operated on a CPU, cause a thread running on the CPU to sleep. However, in the same field of endeavor, EOM teaches the task scheduler comprises a sleep control part configured to, when there is no task to be operated on a CPU, cause a thread running on the CPU to sleep (EOM ¶0005). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify THYAGATURU and JEAUGEY by incorporating the teachings of EOM. The motivation would be to provide fast I/O response time but requires less CPU resources (EOM ¶0005).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over THYAGATURU in view of JEAUGEY, and further in view of Suzuki et (U.S. Patent No. 11,880,611 B2, hereinafter “Suzuki”).
As to claim 7, THYAGATURU as modified by JEAUGEY teaches the accelerator offload system according to claim 6, but fails to teach wherein hardware including the accelerator includes a ring buffer that copies a workload to be processed, and wherein the request I/O part and the response I/O part exchange data with the accelerator via the ring buffer. However, in the same field of endeavor, Suzuki teaches hardware including the accelerator includes a ring buffer that copies a workload to be processed, and wherein the request I/O part and the response I/O part exchange data with the accelerator via the ring buffer (Suzuki Fig. 1, and Col 11 Ln 63 to Col 12 Ln 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify THYAGATURU and JEAUGEY by incorporating the teachings of Suzuki. The motivation would be to efficiently manage a fixed-size, continuous stream of data in a First-In-First-Out (FIFO) manner, ensuring predictable memory usage and fast, constant-time operations (Suzuki Col 11 Ln 18-45).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See Form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER KHONG whose telephone number is (571)270-7127. The examiner can normally be reached Mon-Fri 8am-5pm EST.
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/ALEXANDER KHONG/Primary Examiner, Art Unit 2168
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