DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
In light of the amendment filed 12/3/25, the rejection of claims 1-13 under 35 U.S.C. 112(b) is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi (US 2024/0005861) in view of Cok et al. (US 2010/0123694) and Hashimoto (US 2023/0057215).
Regarding claim 1, Kikuchi discloses a backlight device for a display, comprising: a backlight driving board configured to generate frame-unit backlight data for a backlight and to provide, for each horizontal period, a first column signal and a second column signal having a level corresponding to column data of the backlight data and a row signal corresponding to the horizontal period (fig. 1, figs. 3-5, ¶ 2, ¶ 79-86, peripheral drivers disclosed, gradation controller 40 supplies signals I-Sig and D-Sig, Scanner 30 provides Gate signal; see also ¶ 90-94; see also fig. 12 and ¶ 127-129);
and a backlight board configured to provide the backlight by the first column signal, the second column signal, and the row signal provided for each horizontal period (fig. 22 and ¶ 158-159; fig. 1, figs. 3-5, ¶ 2, ¶ 79-86, gradation controller 40 supplies signals I-Sig and D-Sig, Scanner 30 provides Gate signal; see also ¶ 90-94; see also fig. 12 and ¶ 127-129),
wherein the backlight board comprises: light emitting blocks configured to form columns and rows (fig. 22 and ¶ 158-159; fig. 1, figs. 3-5, ¶ 2, ¶ 79-86);
and current control integrated circuits configured for each control unit and each comprising a plurality of driving current control units configured to receive the first column signal and the second column signal shared by the light emitting blocks of a same column and the row signals corresponding to the plurality of rows, respectively (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate),
wherein each driving current control unit samples the first column signal and the second column signal by using the row signal, and controls an amount of driving current for light emission of the light emitting block to correspond to a pulse width corresponding to a level of a first sampled signal obtained by sampling the first column signal and a level of a second sampled signal obtained by sampling the second column signal (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate).
Kikuchi fails to disclose light emitting blocks to be grouped into a plurality of control units each comprising a plurality of rows, wherein the backlight driving board receives a dimming mode command for defining one of linear control, pulse width control, and composite control, and wherein, in response to the dimming mode command, the backlight driving board provides the first column signal to have a level corresponding to luminance of the backlight and provides the second column signal to have a preset fixed level for the purpose of the linear control, provides the first column signal to have the preset fixed level, provides the second column signal to have the level corresponding to the luminance of the backlight for the purpose of the pulse width control, and provides the first column signal and the second column signal to have the level corresponding to the luminance of the backlight for the purpose of the composite control.
Cok teaches light emitting blocks to be grouped into a plurality of control units each comprising a plurality of rows (figs. 1-2, ¶ 18-27, chiplets for each group 32, see also ¶ 30, ¶ 38).
Kikuchi and Cok are both directed to LED backlight control. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kikuchi with the groups of Cok since such a modification decreases flicker and current densities (Cok, ¶ 30) and the number of connection pads, the number and size of the chiplets, and the cost is reduced (Cok, ¶ 12).
Hashimoto teaches wherein the backlight driving board receives a dimming mode command for defining one of linear control, pulse width control, and composite control (fig. 1, figs. 3-6, ¶ 23-27, ¶ 31-43, see also ¶ 56-64, e.g., gamma curve for PWM and PAM are partially overlapped),
and wherein, in response to the dimming mode command, the backlight driving board provides the first column signal to have a level corresponding to luminance of the backlight and provides the second column signal to have a preset fixed level for the purpose of the linear control (fig. 1, figs. 3-6, ¶ 23-27, ¶ 31-43, e.g., for high grayscale, PWM data is fixed and driving current amplitude is adjusted; see also ¶ 56-64),
provides the first column signal to have the preset fixed level, provides the second column signal to have the level corresponding to the luminance of the backlight for the purpose of the pulse width control (fig. 1, figs. 3-6, ¶ 23-27, ¶ 31-43, e.g., for low grayscale, PWM data is adjusted and driving current amplitude is fixed; see also ¶ 56-64),
and provides the first column signal and the second column signal to have the level corresponding to the luminance of the backlight for the purpose of the composite control (fig. 1, figs. 3-6, ¶ 23-27, ¶ 31-43; e.g., when gray scale is ‘128’, PWM and PAM are fixed at ‘128’; see also ¶ 56-64, e.g., gamma curve for PWM and PAM are partially overlapped).
Kikuchi in view of Cok and Hashimoto are both directed to LED driving using pulse width and pulse amplitude. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kikuchi in view of Cok with the device of Hashimoto since such a modification provides high resolution in the overlapped part (Hashimoto, ¶ 52) and improves optical performance without significantly increasing cost (Hashimoto, ¶ 72).
Regarding claim 2, Kikuchi discloses wherein the backlight driving board receives frame-unit luminance data corresponding to display data (fig. 1, figs. 3-5, ¶ 2, ¶ 79-86, video display via row and column driving disclosed; see also ¶ 90-94; see also fig. 12 and ¶ 127-129; see also ¶ 154, image signal inputted to the electronic apparatus),
generates the frame-unit backlight data for the backlight by using the luminance data (fig. 1, figs. 3-5, ¶ 2, ¶ 79-86, video display via row and column driving disclosed; see also ¶ 90-94; see also fig. 12 and ¶ 127-129; see also ¶ 154, image signal inputted to the electronic apparatus; see also fig. 8, ¶ 116),
generates the first column signal for the linear control and the second column signal for the pulse width control for each horizontal period of the backlight data (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate; see also fig. 8, ¶ 116),
generates the row signal for each horizontal period (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate),
and provides the first column signal, the second column signal, and the row signal (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate).
Regarding claim 4, Cok further teaches wherein the backlight driving board comprises: a microcontroller configured to receive frame-unit luminance data corresponding to display data, to generate the frame-unit backlight data for the backlight by using the luminance data, and to output the horizontal period-by-horizontal period row signal of the frame and first column data and second column data corresponding to the horizontal period-by-horizontal period column data of the backlight data (figs. 1-2, ¶ 18-27, controllers 60 and 50 communicate signals to chiplets 20 via busses 62 and 52, see also ¶ 30, ¶ 38).
Hashimoto further teaches a first digital-to-analog converter configured to receive the first column data and output the first column signal having a level corresponding to the first column data; and a second digital-to-analog converter configured to receive the second column data and output the second column signal having a level corresponding to the second column data (figs. 1-2, ¶ 30, source driver converts PWM data and PAM data with DAC).
Regarding claim 5, Cok further teaches wherein the backlight driving board further comprises a memory, and the microcontroller stores the backlight data for one frame in the memory, reads the backlight data of the memory in units of horizontal periods, and provides the first column data and the second column data (figs. 1-2, ¶ 18-27, storage elements 70, see also ¶ 30, ¶ 38).
Regarding claim 6, this claim is rejected under the same rationale as claim 1.
Regarding claim 7, Kikuchi discloses wherein each driving current control unit generates the first sampled signal by sampling the first column signal by using the row signal and the second sampled signal by sampling the second column signal by using the row signal (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate),
generates a control signal having a current amount at a level corresponding to the first sampled signal and a control pulse having a pulse width corresponding to the second sampled signal (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate),
and controls the amount of the driving current by using the control signal having the current amount controlled by the control pulse (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate; see also fig. 6 and ¶ 114).
Regarding claim 8, Kikuchi discloses wherein each driving current control unit comprises: a first sample and hold unit configured to generate the first sampled signal by sampling the first column signal by using the row signal (figs. 3-5, ¶ 79-86, ¶ 90-94; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate);
a second sample and hold unit configured to generate the second sampled signal by sampling the second column signal by using the row signal (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129);
a voltage current conversion circuit configured to generate a control signal having a current amount corresponding to the level of the first sampled signal (figs. 3-5, ¶ 79-86, ¶ 90-94; see also fig. 12 and ¶ 127-129, modulator 12 receives I-Sig and Gate);
a PWM conversion circuit configured to generate a control pulse having the pulse width corresponding to the level of the second sampled signal (figs. 3-5, ¶ 79-86, ¶ 90-94, controller 13 receives D-Sig and Gate; see also fig. 12 and ¶ 127-129);
a switch configured to switch transmission of the control signal by the control pulse (figs. 3-5, ¶ 79-86, ¶ 90-94; see also fig. 12 and ¶ 127-129, e.g., switches 123, 124);
and a driver configured to control the amount of the driving current for light emission of the light emitting block by the control signal transmitted through the switch (figs. 3-5, ¶ 79-86, ¶ 90-94; see also fig. 12 and ¶ 127-129, e.g., TRout).
Regarding claim 9, Kikuchi discloses wherein the driver comprises a dependent current source connected to a low side of the light emitting block, and the dependent current source controls the amount of the driving current to be proportional to the current amount of the control signal transmitted through the switch (figs. 3-5, ¶ 79-86, ¶ 90-94; see also fig. 12 and ¶ 127-129, TRout controls current based on current modulation signal).
Response to Arguments
Applicant's arguments filed 12/3/25 have been fully considered but they are not persuasive. Regarding claim 1, Applicant argues Hashimoto doesn’t discuss “a discrete mode command that triggers switching among three distinct dimming schemes” and nothing in Hashimoto “discloses or suggests any reception of a command signal, any mode selection, or any mechanism for toggling between three operation modes” (Remarks, pp. 9-10).
Examiner disagrees. As cited above (see Hashimoto, fig. 1, figs. 3-6, ¶ 23-27, ¶ 31-43), Hashimoto teaches, e.g., for high grayscale, PWM data is fixed and driving current amplitude is adjusted; for low grayscale, PWM data is adjusted and driving current amplitude is fixed; and when gray scale is ‘128’, PWM and PAM are fixed at ‘128’ (see also ¶ 56-64, gamma curve for PWM and PAM are partially overlapped in the middle gray scale range).
Thus Hashimoto explicitly teaches three different dimming schemes, namely a first scheme where PWM data is fixed and driving current amplitude is adjusted, a second scheme where PWM data is adjusted and driving current amplitude is fixed, and a third scheme where both PWM and PAM are fixed (or an overlapping range where both PWM and PAM are adjusted in the middle gray scale range, i.e., hybrid). These three different dimming schemes are based on the gray scale data signal DG. For example, if DG is in the ‘low’ range (e.g., below 128), then the light emitting device is driven such that PWM data is adjusted and driving current amplitude is fixed, etc. In other words, the light emitting device is driven based on what range the data signal DG is in, e.g., low, high, or middle (overlapping).
Applicant further argues nowhere in Hashimoto “is there a teaching or suggestion of providing a preset fixed level to either column signal” (Remarks, p. 10). Examiner disagrees. As discussed above, for example, for high grayscale, PWM data is fixed and driving current amplitude is adjusted (see Hashimoto ¶ 31-43).
Applicant’s remaining arguments (see Remarks, last ¶ of p. 9 and last ¶ of p. 10) amount to piecemeal analysis of the references and are not persuasive, as Examiner has relied upon a combination of the references to teach the claimed subject matter.
The rejection of the claims is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626