DETAILED ACTION
Claims 1-19 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claim 1 is independent claims. Claims 2-19 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 09-03-2024.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. It is also noted, that applicant has filed a certified copy on 03-17-2025 as required by 35 U.S.C. 119(b).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09-03-2024 is in compliance with the provisions of 37 CFR 1.97
Claim Objections
Claim 1 recites the term “signalling” in lines 15 and 22. Because of the typographical error, the term should be changed to signaling.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “data storage portion”, “signaling portion” and “data access portion” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
As per dependent claims 2-19, these claims are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Action May Be Required By Applicants
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may do one of the following:
(1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function).
(2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10, 15, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0136737 (hereinafter, “Dreps”) in view of U.S. Publication No. 2016/0261251 (hereinafter, “Tidwell”).
As per claim 1, Dreps discloses a system comprising:
a first circuit portion operating in a first clock domain with a first clock having a first frequency; (Fig. 4 illustrates a circuit having a first clock domain that include variable clock frequency, Alternatively, Fig’s 1, 4, 7)
a second circuit portion operating in a second clock domain with a second clock having a second, higher, frequency; and (Fig. 4 illustrates a circuit having a second clock domain that includes a fixed clock frequency where the “variable frequency is lower than the fixed frequency”, hence making the fixed clock frequency to have a higher frequency. Alternatively, Fig’s 1, 4, 7)
an interface circuit portion for transferring data from the first circuit portion to the second circuit portion, the interface circuit portion comprising: (Fig. 4 illustrates conduits for data transfer between first clock domain and second clock domain. Further examples, ¶ [0020] and Fig’s 1, 4, 7)
a data input arranged to receive data from the first circuit portion; (input ports associated with first and second buffers to receiver data transfer from first clock domain; Fig’s 1, 4, 7)
a data output arranged to provide data to the second circuit portion; (output ports associated with first and second buffers to provide data transfer to the second clock domain; Fig’s 1, 4, 7)
a shared memory comprising a plurality of data storage locations, at any given time one of said data storage locations being allocated as an input data storage location and one of said data storage locations being allocated as an output data storage location, wherein the shared memory is configured to store data asserted at the data input to the input data storage location, and to provide data stored at the output data storage location to the data output; (first buffer and second buffer responsible for data transfer between two clock domain circuits based on whether the asserted mode is synchronous or asynchronous; Fig’s 1-7 )
a data storage portion; (memory regions associated with the first buffer and second buffer; Fig’s 1-7 )
a signaling portion; and (multiplexor; Fig 7)
a data access portion; wherein: (ports for accessing data between first domain and second domain [Fig’s 1-7] or elastic interface 173 operable for receiving data (Fig 7) ) wherein:
the first circuit portion is arranged to assert data at the data input and to assert a data signal when asserting data at the data input. (CPU domain may assert information from register 162 that cause a CPU “grid signal; ¶ [0034])
the data storage portion is configured to detect the data signal and to change the input data storage location in response to the data signal; (¶ [0028] states that “The multiplexor 131 has a mux input port for receiving a first mux command to forward the data from the first buffer 110 further into the second clock domain 130 and a second mux command to forward the data from the second buffer 120 further into the second clock domain 130”. In other words, based on mux command data is transferred from one buffer to another buffer including the elastic interface storage (Fig. 7)
the signaling portion is configured to generate an interface signal and to change a state of said interface signal in response to the data signal; and (¶ [033] states “The multiplexor is operable to forward data from the first buffer 110 or from the second buffer 120 further into the elastic interface 173”.
the data access portion is configured to detect the change of state of the interface signal, (A CPU clock register 162 having a specific value; Fig. 7 ) to change the output data storage location in response to the change of state of the interface signal and to output a data to the second circuit portion in response to the change of state of the interface signal. (¶ [0035] discloses how the multiplexor 131 forwarding the data from the first buffer 110 further into the elastic interface 173 based on register 162 value)
Dreps does not distinctly disclose the following:
a data valid signal; and
a data ready signal.
However, Tidwell explicitly discloses the following:
a data valid signal; and (valid signal; ¶s [0140]-[0144], Fig. 13)
the data access portion (control module 1320; Fig 13) is configured to detect the change of state of the interface signal, (control module may detect signal “levels” associated with a received signal, for example, CS_Sender signal; Fig 13, ¶s [0140]-[0148] ) to change the output data storage location in response to the change of state of the interface signal ( ¶ [0146] states “The control module 1320 may treat that level as qualifying the data that is currently being presented at the output of the multiplexer 1316 as new data for the receiver processing circuit module 1306 to accept.”) and to output a data ready signal to the circuit portion in response to the change of state of the interface signal. (¶ [0141] states “receiver processing circuit block 1306 may be configured to send a receiver ready signal, identified in FIG. 13 as “Rcv_Ready,”)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps and Tidwell because both references are in the same field of endeavor. Tidwell’s teaching of data valid signal and data ready signal would enhance Dreps's system by allowing data transfer to be synchronized, thus enhancing communications between the sender and receiver.
As per claim 2, Dreps as modified discloses a system wherein the number of data storage locations comprised by the shared memory corresponds to a propagation delay between the data valid signal being asserted and the change of state of the interface signal being detected by the data access portion. (Dreps: first and second time delays corresponding to the buffers) & (Tidwell: ¶ [0128] discloses registers 124 may be included to buffer or delay the control signals CS in order to match the delay of buffer circuitry)
As per claim 3, Dreps as modified discloses a system wherein the shared memory consists of four storage portions. (Tidwell: ¶ [0039] discloses a FIFO buffer, that would be apparent to a PHOSITA that a FIFO buffer to include at least 4 memory cells)
As per claim 8, Dreps as modified discloses a system wherein the data access portion comprises a multiplexer configured to connect the data storage location allocated as the output data storage location to the data output. (Dreps: Fig. 7 illustrates a multiplexer) & (Tidwell: Fig 13)
As per claim 9, Dreps as modified discloses a system wherein the data input comprises a plurality of parallel data lines and each of the plurality of data storage locations is configured to store a corresponding plurality of data bits. (Tidwell: n-bit or m-bit register for storing values ¶s [201]-[0205], Fig 13 ) & (Dreps: Fig 7)
As per claim 10, Dreps as modified discloses a system wherein each data storage location comprises a register with an equal number of bits to a number of parallel data lines. (Dreps: registers for CPU domain and I/O domain Fig 7) & (Tidwell: n-bit or m-bit register for storing values ¶s [201]-[0205], Fig 13 )
As per claim 15, Dreps as modified discloses a system wherein the second circuit portion is arranged to access data at the data output in response to the data ready signal output by the data access portion. (Tidwell : ¶ [0141] states “receiver processing circuit block 1306 may be configured to send a receiver ready signal, identified in FIG. 13 as “Rcv_Ready,” & ¶ [0041] states “When processing circuit block B is ready to process the data, processing circuit block B may retrieve the data from its input buffer, which is also FIFO buffer AB.”)
As per claim 17, Dreps as modified discloses a wherein the second circuit portion comprises a data storage device. (Dreps: elastic interface or register; Fig. 7) & (Tidwell: 1306 circuit to process receiver data; Fig. 13)
As per claim 19, Dreps as modified discloses wherein the second circuit portion comprises a data storage interface device. (Dreps: elastic interface or register; Fig. 7) & (Tidwell: 1306 circuit to process receiver data; Fig. 13)
Claims 4-5, 7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0136737 (hereinafter, “Dreps”) in view of U.S. Publication No. 2016/0261251 (hereinafter, “Tidwell”) and further view of U.S. Patent No. 6,408,409 (hereinafter, “Williams”).
As per claim 4, Dreps as modified does not distinctly discloses a system of wherein the shared memory comprises a ring buffer, with each data storage location corresponding to an element of the ring buffer.
However, Williams explicitly discloses a system of wherein the shared memory comprises a ring buffer, with each data storage location corresponding to an element of the ring buffer. (ring buffer 108; Fig 1)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps as modified and Williams because all references are in the same field of endeavor. Williams’s teaching of ring buffer would enhance Dreps's as modified system by operating a more efficient buffer, thus enhancing efficiency for data transfer.
As per claim 5, Dreps as modified discloses a system wherein the data storage portion comprises an incrementer configured to increment a counter value identifying the input data storage location in response to detecting the data valid signal. (Williams: read/write counter; Fig. 2) & (Tidwell: data valid signal; ¶s [0140]-[0144], Fig. 13)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps as modified and Williams because all references are in the same field of endeavor. Williams’s teaching of monitoring counter would enhance Dreps's as modified system by monitoring the state of the buffer, thus preventing error conditions caused by ring buffers.
As per claim 7, Dreps as modified discloses a system wherein the data access portion comprises an incrementer configured to increment a counter value identifying the output data storage location in response to detection of the change of state of the interface signal. (Williams: read/write counter for transferring data through the ring buffer based on the flow indicator value to be stored in the counter ; Fig. 2, abstract)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0136737 (hereinafter, “Dreps”) in view of U.S. Publication No. 2016/0261251 (hereinafter, “Tidwell”) and further view of U.S. Patent No. 9,001,921 (hereinafter, “He”).
As per claim 6, Dreps as modified does not distinctly disclose a system of wherein the data storage portion comprises a demultiplexer configured to connect the data input to the data storage location allocated as the input data storage location.
However, He explicitly discloses a system of wherein the data storage portion comprises a demultiplexer configured to connect the data input to the data storage location allocated as the input data storage location. (demultiplexer to change the state based on incrementer; col 10 lines 0-7)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps as modified and He because all references are in the same field of endeavor. He’s teaching of demultiplexer changing the state based on incrementer would enhance Dreps's as modified system by reducing error rates within a storage buffer, thus enhancing reliability in a computer data system.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0136737 (hereinafter, “Dreps”) in view of U.S. Publication No. 2016/0261251 (hereinafter, “Tidwell”) and further view of U.S. Publication No. 2007/0288874 (hereinafter, “Czeck”).
As per claim 12, Dreps as modified does not distinctly disclose a system wherein the data access portion comprises a plurality of cascaded output flip flops in the second clock domain, wherein a first output flip flop is configured to receive the interface signal as an input.
However, Czeck explicitly discloses the data access portion comprises a plurality of cascaded output flip flops in the second clock domain, wherein a first output flip flop is configured to receive the interface signal as an input. (data access domain B having a cascaded flip flops receiving signal 2; Fig. 2)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps as modified and Czeck because all references are in the same field of endeavor. Czeck’s teaching of implementing a system having cascaded flip flops would enhance Dreps's as modified system by allowing the system to synchronize different clocks for a propagating data signal, thus enhancing data transfer of a system.
Claim(s) 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2014/0136737 (hereinafter, “Dreps”) in view of U.S. Publication No. 2016/0261251 (hereinafter, “Tidwell”) and further view of U.S. Publication No. 2016/0062437 (hereinafter, “Kim”).
As per claim 16, Dreps as modified does not distinctly discloses wherein the first circuit portion comprises a camera device or a camera interface device.
However, Kim Explicitly discloses wherein the first circuit portion comprises a camera device. (camera 200; Fig. 1)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps as modified and Kim because all references are in the same field of endeavor. Kim’s teaching of assigning a separate clock domain to a camera would enhance Dreps's as modified system by allowing the system to control power consumption.
As per claim 18, Dreps as modified discloses wherein the first circuit portion comprises a camera interface device. (camera I/F ; Fig 1)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Dreps as modified and Kim because all references are in the same field of endeavor. Kim’s teaching of assigning a separate clock domain to a camera would enhance Dreps's as modified system by allowing the system to control power consumption.
Allowable Subject Matter Over 35 USC § 102/103
Claims 11 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
Prosecution Insights