DETAILED ACTION
This is in response to communication filed on 12/8/2025.
Status of Claims
Claims 1 – 4 and 6 – 23 are pending, of which claims 1, 22, and 23 are in independent form.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/8/2025 and 1/13/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
In light of applicant’s amendments to the drawings, the examiner withdraws the previous objection to the drawings.
Specification
In light of applicant’s amendments to the specification, the examiner withdraws the previous objection to the specification.
Claim Objections
In light of applicant’s amendments to claims 1, 22, and 23, the examiner withdraws the previous objection to these claims.
Claim 4 remains objected to because of the following informalities: claim 4 line 3 states “the same” when the claim should state “a same.” Appropriate correction is required.
Claim 7 is objected to because of the following informalities: claim 7 depends from cancelled claim 5. Appropriate correction is required.
Claim Rejections - 35 USC § 112
In light of applicant’s amendments to the claims, the examiner withdraws the previous rejection under 35 USC 112 to claim 3.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 5 – 9, 13 – 14, and 22 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Thorson et al., U.S. Patent Application 2018/0285316 (hereinafter referred to as Thorson) in view of Linford et al., ‘Intro to SVE: Arm SVE Fundamentals’ (hereinafter referred to as Linford).
Regarding claim 1, Thorson teaches an apparatus comprising: processing
circuitry to perform data processing (Figure 2 and [0044-0046]: vector reduction unit
212 performs operations including "a summation vector reduction, maximum or
minimum value vector reduction, or maximum or minimum index vector reduction", i.e.
data processing); and instruction decoding circuitry to control the processing
circuitry to perform the data processing in response to decoding of program
instructions ... (Figure 2 and [0039-0040] teaches a sequencer 206, i.e. decoder,
which receives instructions from the host interface, converts them to low-level control
signals, and directs processing circuitry to execute operations); in which: the
instruction decoding circuitry and the processing circuitry are configured to
support a sub-vector-supporting instruction which treats a given vector as
comprising a plurality of sub-vectors with each sub-vector comprising a plurality
of vector elements ... ([0039] "The sequencer 206 may receive an instruction to initiate
a vector reduction computation on the circuit 200, and may generate a control signal for
controlling a vector reduction unit 212 to initiate the vector reduction computation" and
[0025] "an input vector may be segmented, and respective vector reduction operations
may be performed on one or more of the segments of the input vector"; in other words,
the vector has segments which correspond to the claimed sub-vectors and segments
contain elements); and in response to the sub-vector-supporting instruction, the
instruction decoding circuitry is configured to control the processing circuitry to
perform an operation for the given vector at sub-vector granularity ([0039] "The
sequencer 206 may receive an instruction to initiate a vector reduction computation on
the circuit 200, and may generate a control signal for controlling a vector reduction unit
212 to initiate the vector reduction computation" and [0002] teaches that operations may
be performed on multiple segments of an input vector, i.e. segment/sub-vector
granularity: "for example, a segmented summation vector reduction operation may
produce an output vector in which each element is a sum of a segment of elements of
the input vector").
Thorson does not explicitly teach program instructions defined according to a
scalable vector instruction set architecture supporting vector instructions operating on
vectors of scalable vector length to enable a same instruction sequence to be
executed on apparatuses with hardware supporting different maximum vector lengths
and each sub-vector having an equal sub-vector length.
Linford teaches program instructions defined according to a scalable vector
instruction set architecture supporting vector instructions operating on vectors
of scalable vector length to enable a same instruction sequence to be executed
on apparatuses with hardware supporting different maximum vector lengths
(Slide 2 shows that "The exact same binary code runs on hardware with different vector
lengths". An operation is performed on vector A with vector B resulting in output vector
C, and it is shown that this works with different vector lengths including 512 bit vector
unit and 256 bit vector unit. In other words, hardware with different maximum vector
lengths are supported, and the instruction sequence is represented by binary code.
These instructions are therefore part of a scalable instruction set architecture and is
further supported by Slide 2 stating that "Arm's Scalable Vector Extension" is "an ISA
feature which Si partners can implement at length -128 to 2048 bits") each sub-vector
having an equal sub-vector length (Slide 5 teaches that an SVE vector can be "any
multiple of 128 bits up to 2048 bits" and slide 7 teaches "Z0-Z31 extending NEON's
128-bit V0-V31 ". In other words, SVE defines an architectural increment of 128 bits, so
Z vectors are composed of equal-sized 128-bit blocks, interpreted as equal length subvectors).
Linford further teaches each subvector has a sub-vector length, defining the sub-vector granularity at which the operation is performed, where the sub-vector length is of an architecturally-defined fixed size which is independent of a vector length used for the given vector (slide 5 teaches that an SVE vector can be "any multiple of 128 bits up to 2048 bits" and slide 7 teaches "Z0-Z31 extending NEON's 128-bit V0-V31". In other words, 128-bit vectors in the Z vectors are interpreted as equal length sub-vectors, which is an architecturally-defined fixed size because it corresponds to NEON architecture. This size is fixed and is independent of the scalable Z vector length. Slide 4 shows the granularity of execution based on the 128-bit sub-vectors).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson by incorporating the
teachings of Linford to include that the program instructions of Thorson are defined
according to a scalable vector instruction set architecture of Linford, supporting vector
instructions operating on vectors of scalable vector length to enable the same
instruction sequence to be executed on apparatuses with hardware supporting different
maximum vector lengths and each sub-vector having an equal sub-vector length defining the sub-vector granularity at which the operation is performed.
Doing so would allow for improved portability and reuse of program code across hardware implementations with varying vector widths. Doing so would also have simplified hardware design and instruction semantics by ensuring consistent partitioning of vectors into fixed-size increments, thereby facilitating mapping of legacy 128-bit SIMD code (i.e. NEON architecture) into the scalable SVE framework.
Regarding claim 2, Thorson in view of Linford teaches the apparatus
according to claim 1. Thorson in view of Linford further teaches in which each subvector has the sub-vector length which is known at compile time for a given
instruction sequence to be executed using the sub-vector-supporting instruction
(Linford slide 5 teaches that an SVE vector can be "any multiple of 128 bits up to 2048
bits" and Linford slide 7 teaches "Z0-Z31 extending NEON's 128-bit V0-V31". In other
words, 128-bit vectors in the Z vectors are interpreted as equal length sub-vectors,
which is known at compile time because SVE explicitly defines Z vectors as multiples of
128 bit blocks).
Regarding claim 3, Thorson in view of Linford teaches the apparatus according to claim 1. Thorson in view of Linford further teaches in which how many
sub-vectors are comprised by the given vector is unknown at compile time for the
given instruction sequence (Linford slide 2, "The hardware sets the vector length ...
In software, vectors have no length ... The exact same binary code runs on hardware
with different vector lengths". In other words, SVE instructions are designed to operate
on vectors of unknown length, the com piled binary doesn't need to be recompiled or
rewritten for different vector sizes, i.e. amount of sub-vectors comprised in the vector.
The hardware handles the actual vector width, and the software adapts automatically).
Regarding claim 4, Thorson in view of Linford teaches the apparatus
according to claim 1. Thorson in view of Linford further teaches in which in response
to the sub-vector-supporting instruction, the instruction decoding circuitry is
configured to control the processing circuitry to process each of the sub-vectors
in response to the same instance of executing the sub-vector-supporting
instruction (Thorson [0002] "a segmented vector reduction operation produces an
output vector in which each element is a reduction of a segment of the input vector. For
example, a segmented summation vector reduction operation may produce an output
vector in which each element is a sum of a segment of elements of the input vector").
Regarding claim 6, Thorson in view of Linford teaches the apparatus
according to claim 5. Thorson in view of Linford further teaches in which the
architecturally-defined fixed size corresponds to an architecturally-defined
maximum vector length prescribed for vector instructions processed according
to a predetermined non-scalable vector instruction set architecture (Linford slide 5
teaches that an SVE vector can be "any multiple of 128 bits up to 2048 bits" and Linford
slide 7 teaches "Z0-Z31 extending NEON's 128-bit V0-V31". In other words, 128-bit
vectors in the Z vectors are interpreted as equal length sub-vectors, which is an
architecturally-defined fixed size because it corresponds to NEON architecture, and is a
non-scalable vector ISA with 128-bit maximum vector length).
Regarding claim 7, Thorson in view of Linford teaches the apparatus
according to claim 5 (cancelled). Thorson in view of Linford further teaches in which the architecturally-defined fixed size is 128 bits (Linford slide 5 teaches that an SVE
vector can be "any multiple of 128 bits up to 2048 bits" and Linford slide 7 teaches "Z0-
Z31 extending NEON's 128-bit V0-V31". In other words, 128-bit vectors in the Z vectors
are interpreted as equal length sub-vectors, which is an architecturally-defined fixed
size because it corresponds to NEON architecture, and is a non-scalable vector ISA
with 128-bit maximum vector length).
Regarding claim 8, Thorson in view of Linford teaches the apparatus
according to claim 1. Thorson in view of Linford further teaches in which each vector
element of each sub-vector has a variable element size, and the sub-vector length
is independent of which element size is used for each vector element within each
sub-vector (Linford, slide 7, "Scalable vector registers ... Z0-Z31 extending NEON's
128-bit V0-V31 ... Packed DP, SP & HP floating-point elements ... Packed 64, 32, 16 &
8-bit integer elements". In other words, the 128 bit fixed sub-vector length as described
in claim 1 is independent of the variable element size).
Regarding claim 9, Thorson in view of Linford teaches the apparatus
according to claim 1. Thorson in view of Linford further teaches in which for at least
one sub-vector-supporting instruction, the operation performed at sub-vector
granularity is an operation performed, for each sub-vector, on vector elements
within that sub-vector, independent of elements in other sub-vectors (Thorson
[0002] "a segmented vector reduction operation produces an output vector in which
each element is a reduction of a segment of the input vector. For example, a segmented
summation vector reduction operation may produce an output vector in which each
element is a sum of a segment of elements of the input vector").
Regarding claim 13, Thorson in view of Linford teaches the apparatus
according to claim 1. Thorson in view of Linford further teaches in which, in
response to a sub-vector-supporting reduction instruction, the instruction
decoder is configured to control the processing circuitry to perform at least one
reduction operation at sub-vector granularity, each reduction operation to reduce
a plurality of vector elements of an operand vector to a single data value within a
result (Thorson [0002] "a segmented vector reduction operation produces an output
vector in which each element is a reduction of a segment of the input vector. For
example, a segmented summation vector reduction operation may produce an output
vector in which each element is a sum of a segment of elements of the input vector").
Regarding claim 14, Thorson in view of Linford teaches the apparatus
according to claim 13, in which, for an intra-sub-vector sub-vector-supporting
reduction instruction, for each reduction operation the plurality of vector
elements comprise the respective vector elements within a corresponding sub-vector of the operand vector (Thorson [0002] "a segmented vector reduction
operation produces an output vector in which each element is a reduction of a segment
of the input vector. For example, a segmented summation vector reduction operation
may produce an output vector in which each element is a sum of a segment of elements
of the input vector").
Regarding claim 22, the claim recites a method which is similar to the apparatus
of claim 1 and is therefore rejected on the same premises.
Regarding claim 23, the claim is a product claim that is similar and therefore
mostly rejected for the same reasons as the apparatus of claim 1.
Thorson further teaches a non-transitory storage medium storing a computer
program to control a host data processing apparatus to provide an instruction
execution environment for execution of target code ([0097] "Embodiments of the
subject matter described in this specification can be implemented as one or more
computer programs, i.e., one or more modules of computer program instructions
encoded on a tangible non transitory program carrier for execution by, or to control the
operation of, data processing apparatus" and [0098] "the apparatus can also include, in
addition to hardware, code that creates an execution environment for the computer
program in question, e.g., code that constitutes processor firmware, a protocol stack, a
database management system, an operating system, or a combination of one or more
of them").
Claims 10, 12, and 16 is/are rejected under 35 U.S.C. 103 as being
unpatentable over Thorson et al. (US 20180285316 A1) in view of Linford et al.
(Intro to SVE: Arm SVE Fundamentals) in further view of Arm Limited (Arm C
Language Extensions for SVE version 00bet6).
Regarding claim 10, Thorson in view of Linford teaches the apparatus
according to claim 1.
Thorson in view of Linford does not explicitly teach in which for at least one subvector-supporting instruction, the operation performed at sub-vector granularity is an
operation performed, for each element position within a sub-vector, on respective vector
elements at that element position within each of the plurality of sub-vectors.
Arm Limited teaches in which for at least one sub-vector-supporting
instruction, the operation performed at sub-vector granularity is an operation
performed, for each element position within a sub-vector, on respective vector
elements at that element position within each of the plurality of sub-vectors
(Pages 230-231, "7.5.7. ZIP1 Q: Interleave quadwords from low halves of two inputs
These functions map to the .Q form of the ZIP1 instruction. If the vector length is a
multiple of 256 bits, the functions extract 128-bit quadwords from the lowest-indexed
halves of two vectors and interleave them, so that each low quadword of the first input is
followed by the corresponding quadword of the second input. See the architecture
documentation for a description of the behavior for other vector lengths. Although there
is one instance of this operation for every vector type, the results are bitwise identical";
in other words, these permutes work by taking elements from corresponding positions in
each sub-vector and interleaving/rearranging them).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Arm Limited to support operations which for at least one
sub-vector-supporting instruction, the operation performed at sub-vector granularity is
an operation performed, for each element position within a sub-vector, on respective
vector elements at that element position within each of the plurality of sub-vectors.
Doing so would have improved the flexibility of the reduction and permutation circuitry to handle not only operations within each sub-vector but also operations across subvectors. This would have enhanced compatibility with the scalable vector ISA by
enabling a broader set of sub-vector instructions.
Regarding claim 12, Thorson in view of Linford teaches the apparatus
according to claim 1. Although Thorson teaches providing "the reduction of the input vector to a permute circuit configured to compute vector or matrix permutations" [0012], Thorson in view of Linford is not used for the permute instruction where in response to a subvector-supporting permute instruction, the instruction decoder is configured to control the processing circuitry to set, for each sub-vector of a vector result, the sub-vector to a permutation of one or more vector elements selected from among vector elements within a correspondingly-positioned sub-vector of at least one vector operand.
Arm Limited teaches in response to a sub-vector-supporting permute
instruction, the instruction decoder is configured to control the processing
circuitry to set, for each sub-vector of a vector result, the sub-vector to a
permutation of one or more vector elements selected from among vector
elements within a correspondingly-positioned sub-vector of at least one vector
operand (Pages 230-231, "7.5.7. ZIP1 Q: Interleave quadwords from low halves of two
inputs These functions map to the .Q form of the ZIP1 instruction. If the vector length is
a multiple of 256 bits, the functions extract 128-bit quadwords from the lowest-indexed
halves of two vectors and interleave them, so that each low quadword of the first input is
followed by the corresponding quadword of the second input. See the architecture
documentation for a description of the behavior for other vector lengths. Although there
is one instance of this operation for every vector type, the results are bitwise identical";
in other words, these permutes work by taking elements from corresponding positions in
each sub-vector and interleaving/rearranging them).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Arm Limited to support operations such as a sub-vector-supporting permute instruction, where the instruction decoder is configured to control
the processing circuitry to set, for each sub-vector of a vector result, the sub-vector to a
permutation of one or more vector elements selected from among vector elements
within a correspondingly-positioned sub-vector of at least one vector operand. Doing so
would enable the reduction/permute pipeline to place reduction results into desired
element positions within correspondingly-positioned sub-vectors, thereby increasing
flexibility and compatibility with scalable vector ISAs.
Regarding claim 16, Thorson in view of Linford teaches the apparatus
according to claim 1.
Thorson in view of Linford does not explicitly teach in which in response to a subvector-supporting load/store instruction, the instruction decoder is configured to control the processing circuitry to perform a load/store operation to transfer, at sub-vector granularity, one or more sub-vectors between a memory system and at least one vector register.
Arm Limited teaches in which in response to a sub-vector-supporting
load/store instruction, the instruction decoder is configured to control the
processing circuitry to perform a load/store operation to transfer, at sub-vector
granularity, one or more sub-vectors between a memory system and at least one
vector register (Page 49, "6.2.8. LD1 RQ: Unextended load and replicate to quadword
These functions load 128 bits of data under predicate control, setting inactive elements
in the 128 bits to zero. The functions then duplicate the data to every 128-bit quadword
of the vector result").
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Arm Limited to support an instruction which performs a
load/store operation to transfer, at sub-vector granularity, one or more sub-vectors
between a memory system and at least one vector register. Doing so would have
enabled the apparatus to further support scalable memory operations that operate at
sub-vector granularity defined by the scalable vector ISA thereby improving
compatibility with SVE-style instructions.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over
Thorson et al. (US 20180285316 A1) in view of Linford et al. (Intro to SVE: Arm
SVE Fundamentals) in further view of Stephens et al. (US 20180210733 A1).
Regarding claim 11, Thorson in view of Linford teaches the apparatus
according to claim 1.
Thorson in view of Linford further teaches in which for at least one sub-vectorsupporting instruction, the operation performed at sub-vector granularity is an operation (Thorson [0002] "a segmented vector reduction operation produces an output vector in which each element is a reduction of a segment of the input vector. For
example, a segmented summation vector reduction operation may produce an output
vector in which each element is a sum of a segment of elements of the input vector").
Thorson in view of Linford does not explicitly teach an operation to set, or
perform an operation depending on, selected predicate bits of a predicate value, where
the selected predicate bits are predicate bits corresponding to sub-vector-sized portions
of a vector.
Stephens teaches an operation to set, or perform an operation depending
on, selected predicate bits of a predicate value, where the selected predicate bits
are predicate bits corresponding to sub-vector-sized portions of a vector ([0025]
"Whilst in one embodiment there may be a 1 :1 relationship between the number of
items of predicate conditions within the predicate data and the number of data elements
in an associated vector controlled by that predicate data, this is not essential, and in
alternative embodiments a single item of predicate data may provide a condition which
is applied to multiple data elements"; in other words, a single predicate item may control
multiple data elements which corresponds to applying a predicate bit at the granularity
of a sub-vector, since each sub-vector comprises multiple data elements).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Stephen to include an operation to set, or perform an
operation depending on, selected predicate bits of a predicate value, where the selected
predicate bits are predicate bits corresponding to sub-vector-sized portions of a vector.
Doing so would have enabled the apparatus to support predicate operations at sub-vector granularity consistent with the scalable vector ISA, thereby providing better
control over which sub-vectors participate in a given operation.
Claims 15 and 17-21 is/are rejected under 35 U.S.C. 103 as being
unpatentable over Thorson et al. (US 20180285316 A1) in view of Linford et al.
(Intro to SVE: Arm SVE Fundamentals) in further view of Steuben et al.
(TOWARDS REAL-TIME COMPOSITE MATERIAL CHARACTERIZATION USING
SURROGATE MODELS AND GPGPU COMPUTING).
Regarding claim 15, Thorson in view of Linford teaches the apparatus
according to claim 13. Thorson in view of Linford does not explicitly teach in which, for an inter-subvector sub-vector-supporting reduction instruction, for each reduction operation the plurality of vector elements comprise the vector elements at corresponding element positions within a plurality of sub-vectors of the operand vector.
Steuben teaches in which, for an inter-sub-vector sub-vector-supporting
reduction instruction, for each reduction operation the plurality of vector
elements comprise the vector elements at corresponding element positions
within a plurality of sub-vectors of the operand vector (Page 9, figure 8 shows an
"illustration of the optimized parallel reduce algorithm" with an input data vector having
data values, where an initial stride of 8 is used to reduce corresponding element
positions. In other words, the strided reduction on the input vector is interpreted as a
reduction across sub-vectors and the reduction step 1 is interpreted as the result of the
reduction operation).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Steuben to include for an inter-sub-vector sub-vector-supporting reduction instruction, for each reduction operation the plurality of vector
elements comprise the vector elements at corresponding element positions within a
plurality of sub-vectors of the operand vector. Doing so would have allowed the
apparatus to support inter-sub-vector reductions, thereby broadening the reduction
capabilities beyond intra-sub-vector operations.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over
Thorson et al. (US 20180285316 A1) in view of Linford et al. (Intro to SVE: Arm
SVE Fundamentals) in further view of Arm Limited (Arm C Language Extensions
for SVE version 00bet6) in further view of Stephens et al. (US 20180210733 A1).
Regarding claim 17, Thorson in view of Linford in view of Arm Limited teaches
the apparatus according to claim 16.
Although Arm Limited teaches predicate control, the LD1 RQ describes
predication in terms of elements and therefore does not explicitly teach in which the
sub-vector-supporting load/store instruction is a predicated instruction associated with a
predicate value; and in response to the sub-vector-supporting load/store instruction, the
instruction decoder is configured to control the processing circuitry to control, based on
predicate bits selected from the predicate value at sub-vector granularity, whether each
transfer of the one or more sub-vectors is performed or masked.
Stephens teaches in which the sub-vector-supporting load/store instruction
is a predicated instruction associated with a predicate value; and in response to
the sub-vector-supporting load/store instruction, the instruction decoder is
configured to control the processing circuitry to control, based on predicate bits
selected from the predicate value at sub-vector granularity, whether each transfer
of the one or more sub-vectors is performed or masked ([0025] "Whilst in one
embodiment there may be a 1 :1 relationship between the number of items of predicate
conditions within the predicate data and the number of data elements in an associated
vector controlled by that predicate data, this is not essential, and in alternative
embodiments a single item of predicate data may provide a condition which is applied to
multiple data elements"; in other words, a single predicate item may control multiple
data elements which corresponds to applying a predicate bit at the granularity of a subvector, since each sub-vector comprises multiple data elements).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Stephens to include whether each transfer of the one or
more sub-vectors is performed or masked based on predicate bits selected from the
predicate value at sub-vector granularity. Doing so would have enabled the apparatus to
support predicate memory transfers at sub-vector granularity consistent with the
scalable vector ISA, thereby providing better control over which sub-vectors participate
in a given transfer.
Regarding claim 18, Thorson in view of Linford teaches the apparatus
according to claim 1.
Thorson in view of Linford does not explicitly teach in which in response to a subvector-supporting increment/decrement instruction, the instruction decoder is configured to control the processing circuitry to increment or decrement an operand value based on how many sub-vector-sized portions of a vector are indicated as active by bits of a predicate value selected from the predicate value at sub-vector granularity
Arm Limited teaches in which in response to a sub-vector-supporting
increment/decrement instruction, the instruction decoder is configured to control
the processing circuitry to increment or decrement an operand value based on
how many element-sized portions of a vector are indicated as active by bits of a
predicate value selected from the predicate value at element granularity (Page 215
"6.28.5. QINCP: Saturating increment by a multiple of svcntp These functions pass the
second input to svcntp and add the result to the first input. The addition is saturating, so
if the sum is outside the range of the return type, the result is the nearest in-range
value." where svcntp refers to Page 210 "6.27.1. CNTP: Count active elements These
functions count the number of active elements in a predicate input. A numerical suffix
indicates the size of data that the predicate controls"; in other words, inputs are
interpreted as operand values of the instruction).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford by
incorporating the teachings of Stephen to include in response to a sub-vector-supporting increment/decrement instruction, the instruction decoder is configured to
control the processing circuitry to increment or decrement an operand value based on
how many element-sized portions of a vector are indicated as active by bits of a
predicate value selected from the predicate value at element granularity. Doing so
would have enabled the apparatus to support increment and decrement operations
controlled by predication, thereby extending the segmented vector operations. This
would have improved efficiency of implementing predicated loops and control flow by
allowing operand values to be adjusted automatically based on the number of active
predicate bits.
However, Arm Limited teaches that the svcntp function counts active elements
instead of active sub-vector-sized portions.
Stephens teaches sub-vector-sized portions of a vector are indicated as
active by bits of a predicate value selected from the predicate value at sub-vector
granularity ([0025] "Whilst in one embodiment there may be a 1 :1 relationship between the number of items of predicate conditions within the predicate data and the number of data elements in an associated vector controlled by that predicate data, this is not essential, and in alternative embodiments a single item of predicate data may provide a condition which is applied to multiple data elements"; in other words, a single predicate item may control multiple data elements which corresponds to applying a predicate bit at the granularity of a sub-vector, since each sub-vector comprises multiple data elements).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford in further
view of Arm Limited to incorporate the teachings of Stephens include that sub-vectorsized portions of a vector are indicated as active by bits of a predicate value selected from the predicate value at sub-vector granularity. Doing so would have further enabled the apparatus to perform predicated increment and decrement operations at sub-vector granularity, improving compatibility with scalable vector ISAs by allowing predicate bits to represent activity at the level of equal sized sub-vectors.
Regarding claim 19, Thorson in view of Linford in further view of Arm Limited in
further view of Stephens teaches the apparatus according to claim 18. Thorson in
view of Linford in further view of Arm Limited in further view of Stephens further teaches
in which the predicate value is one of: a predicate value specified as a predicate
operand by the sub-vector-supporting increment/decrement instruction; and a
predicate value implied by a predicate pattern identifier specified by the subvector-supporting increment/decrement instruction, the predicate pattern
identifier specifying a predetermined pattern of predicate bits at sub-vector
granularity (Arm Limited page 215, 6.28.5.1 and 6.28.5.2 use svbool_t pg as an
operand of the svqincp instruction which is the predicate input).
Regarding claim 20, Thorson in view of Linford teaches the apparatus
according to claim 1.
Thorson in view of Linford does not explicitly teach in response to a sub-vector-supporting predicate setting instruction, the instruction decoder is configured to control the processing circuitry to perform a predicate setting operation to set bits of a predicate value at sub-vector-granularity, to indicate which sub-vectors of a vector are active.
Arm Limited teaches in which in response to a sub-vector-supporting
predicate setting instruction, the instruction decoder is configured to control the
processing circuitry to perform a predicate setting operation to set bits of a
predicate value at element-granularity, to indicate which elements of a vector are
active (Page 204 "6.23.1. PTRUE: Return an all-true predicate for a given pattern ...
These functions return an all-true predicate for a particular vector pattern and element
size. When an element has more than one predicate bit associated with it, only the
lowest of those bits is ever true. There are two forms: one with a _pat suffix that takes
an explicit vector pattern and one without a _pat suffix in which the pattern is implicitly
SV_ALL").
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford to
incorporate the teachings of Arm Limited to include in response to a sub-vector-supporting predicate setting instruction, the instruction decoder is configured to control
the processing circuitry to perform a predicate setting operation to set bits of a predicate
value at element-granularity, to indicate which elements of a vector are active. Doing so
would have enabled the apparatus to support predicate setting instructions thereby
extending segmented operations and improving flexibility in controlling which elements
participate in vector operations through architecturally defined predicate instructions.
However, Arm Limited does not explicitly teach setting bits of a predicate value at
sub-vector-granularity, to indicate which sub-vectors of a vector are active for the
PTRUE function.
Stephens teaches setting bits of a predicate value at sub-vector-granularity,
to indicate which sub-vectors of a vector are active ([0025] "Whilst in one
embodiment there may be a 1 :1 relationship between the number of items of predicate
conditions within the predicate data and the number of data elements in an associated
vector controlled by that predicate data, this is not essential, and in alternative
embodiments a single item of predicate data may provide a condition which is applied to
multiple data elements"; in other words, a single predicate item may control multiple
data elements which corresponds to applying a predicate bit at the granularity of a subvector, since each sub-vector comprises multiple data elements).
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Thorson in view of Linford in further
view of Arm Limited to incorporate the teachings of Stephens to include setting bits of a
predicate value at sub-vector-granularity, to indicate which sub-vectors of a vector are
active. Doing so would have enabled the apparatus to support predicate setting
operations at sub-vector granularity consistent with the scalable vector ISA, thereby
providing better control over which sub-vectors participate in a given operation.
Regarding claim 21, Thorson in view of Linford in further view of Arm Limited in
further view of Stephens teaches the apparatus according to claim 20. Thorson in
view of Linford in further view of Arm Limited in further view of Stephens further
teaches in which the predicate setting operation comprises setting the predicate
value based on one of: a predicate pattern identifier specifying a predetermined
pattern of predicate bits to be applied at sub-vector granularity; and sub-vector-granularity comparison operations based on a comparison of a first operand and
a second operand (Page 204 "6.23.1. PTRUE: Return an all-true predicate for a given
pattern ... These functions return an all-true predicate for a particular vector pattern and
element size. When an element has more than one predicate bit associated with it, only
the lowest of those bits is ever true. There are two forms: one with a _pat suffix that
takes an explicit vector pattern and one without a _pat suffix in which the pattern is
implicitly SV_ALL"; in other words, an explicit vector pattern is used to set the predicate
value).
Response to Arguments
Applicant's arguments filed 12/8/2025 have been fully considered but they are not persuasive.
Applicant argues, on pages 10 – 11 that
The proposed combination of Thorson and Linford does not disclose or suggest: "each sub-vector has a sub-vector length, defining the sub-vector granularity at which the operation is performed, where the sub-vector length is of an architecturally-defined fixed size which is independent of a vector length used for the given vector." This claim language specifies that the operation is performed at sub-vector granularity defined by a sub-vector length of an architecturally-defined fixed size, which is independent of the vector length of the vector.
The rejection of claim 5 on page 12 of the OA states that Linford teaches that an SVE vector can be any multiple of 128 bits and asserts that 128 bits corresponds to an architecturally-defined fixed size. However, this does not teach the quoted claim feature because the 128-bit size in Linford does not define the sub-vector granularity at which the operation is performed. Thus, the OA's assertion a 128-bit size is not relevant to the claim feature which relates to the granularity at which the operation is performed.
The examiner disagrees. As above, Linford teaches that an SVE vector can be "any multiple of 128 bits up to 2048 bits" and slide 7 teaches "Z0-Z31 extending NEON's 128-bit V0-V31". In other words, 128-bit vectors in the Z vectors are interpreted as equal length sub-vectors, which is an architecturally-defined fixed size because it corresponds to NEON architecture. This size is fixed and is independent of the scalable Z vector length. Slide 4 shows the granularity of execution based on the 128-bit sub-vectors.
Applicant argues, on page 11 that
Linford describes Arm's SVE architecture where the granularity at which the operation is performed is that of the full vector length, which is not architecturally-defined to be a fixed size, but by definition is implementation-dependent (see slide 5 of Linford). The 128-bit size mentioned in Linford plays no role in defining the granularity with which operations are performed on the vector. The 128-bit size simply defines the range of options available to an implementation provider for choosing the full vector length but does not constrain the granularity at which operations are performed on the vector. In Linford, the granularity of the operation is dependent on the full vector length.
In contrast, the claimed operation is performed at a sub-vector granularity which is independent of the vector length used for the given vector and is also specified as an architecturally-defined fixed size.
The examiner disagrees. As above, Linford teaches that an SVE vector can be "any multiple of 128 bits up to 2048 bits" and slide 7 teaches "Z0-Z31 extending NEON's 128-bit V0-V31". In other words, 128-bit vectors in the Z vectors are interpreted as equal length sub-vectors, which is an architecturally-defined fixed size because it corresponds to NEON architecture. This size is fixed and is independent of the scalable Z vector length. Slide 4 shows the granularity of execution based on the 128-bit sub-vectors. As seen in slide 4, the 128 bit sub-vectors do not change and slide 3 shows that the SVE is vector length agnostic.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
‘THE ARM SCALABLE VECTOR EXTENSION’ by Nigel Stephens et al., copyright 2017, IEEE teaches the vector length is an implementation choice and states “SVE provides the capabilities for software to be vector-length agnostic through the use of vector partitioning while also supporting more conventional SIMD coding styles that require fixed-length, multiple-of-N, or power-of-two subvectors.”
Contact Information
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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