DETAILED ACTION
The current Office Action is in response to the papers submitted 04/28/2026. Claims 1 – 2 and 4 - 19 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 18 discloses the activated lock setting circuit is configured to cause an external device accessing the memory card to output an error message in response to the received lock control signal. This limitation is not supported by the original specification. An “error message” is only disclosed once in the specification in paragraph 100. Paragraph 100 describes a camera that cannot access the memory card and an error message is output. There is no indication of where the error message is output from on displayed on. There is also no mention of any particular circuit on either the camera or the memory card that generates or causes the error message to be output. The claimed limitation of the lock setting circuit causing an error message to be output is not supported.
Claim 19 contains similar language rejected above in claim 18 and is rejected for similar reasons.
Claims 18 - 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the activated lock setting circuit" in line 1. There is no previous disclosure of a lock setting circuit being activated in the claim or any base claim. Claim 1 does disclose a signal that is configured to activate a lock setting circuit based on a remaining lifetime value. However, claim 1 does not positively state that the lock control signal is generated and that the lock setting circuit is actually activated. Claim 1 merely discloses what may happen in the future but never positively states that it happens, therefor there is no activated lock setting circuit. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 discloses “an external device accessing the memory card” in line 2. It is unclear what the scope of external is in the claim. Base claim 1 discloses a memory card reader that is coupled to the memory card. It is unclear if the external device includes the memory card, the memory card reader, another device, or circuit in the claims. It is unclear what the external device is external to exactly. For examination the limitation will be treated as any device that accesses the memory card.
Claim 18 discloses “the received lock control signal” in line 3. Base claim 1 discloses an alarm circuit configured to transmit a lock control signal to the memory card based on a certain condition. There is no limitation that the condition is even met or that the lock control signal is actually ever sent. There is also no recitation in claim 18 or base claim 1 that a transmitted lock control signal is actually received. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 contains similar language rejected above in claim 18 and is rejected for similar reasons based on the relationship of claims 4 and 19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, 14, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parulski et al. (Pat 5,633,678) referred to as Parulski in view of Yasukawa (Pub. No.: US 2019/0187926) referred to as Yasukawa in view of Lee et al. (Pub. No.: US 2015/0339070) referred to as Lee in view of Reimers (Pub. No.: US 2017/0097781) referred to as Reimers.
Regarding claim 1, Parulski teaches a memory card reader [Fig 2; The camera reads a memory card making the camera a memory card reader] equipped with a self-data deletion and optimization function [52f, Fig 3; 63, Fig 4; 75, Fig 5; The camera deletes data and optimizes data by removing unwanted data], the memory card reader [Fig 2] comprising:
a first terminal [26, Fig 2] configured to be coupled to a memory card [24, Fig 2] and to electrically connect the memory card [24, Fig 2] to components of the memory card reader [Fig 2; The memory card is connected to every other component of the camera through item 26];
a button configured to be manipulated by a user to generate a command [21, Fig 2; 54 and 56, Fig 3; Multiple buttons are used by a user to generate commands to operate the camera] for operating the memory card reader [Fig 2];
a display configured to display information [50, Fig 3] related to an operation of the memory card reader [Fig 2];
a second terminal configured to be coupled to an external computing device [64, Figs 4 - 5; Connecting the camera to a host computer shows a second terminal configured for the connection] and to electrically connect the memory card [24, Fig 2] to the external computing device [66, Figs 4 – 5, Data being downloaded from the memory card to the host computer shows an electrical connection between the memory card and the external computing device through the connection to the host computer]; and
a processor [20, Fig 2; The processor is directly or indirectly connected to every other device in the camera] electrically connected to the first terminal [26, Fig 2], the button [21, Fig 2; 54 and 56, Fig 3], the display [50, Fig 3], and the second terminal [64, Figs 4 – 5], the processor [20, Fig 2] being configured to control the operation of the memory card reader [Fig 2; Column 4, Lines 3 – 22; Column 5, Lines 32 – 52; The processor controls the operations of the camera],
wherein the button [21, Fig 2; 54 and 56, Fig 3] is configured to select a first algorithm for data deletion and optimization [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; One or more buttons are used to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card] which is stored in the memory card reader [31, Fig 2; Column 5, Lines 32 – 51; Item 31 stores instructions that are executed to operate the camera], and
the processor [20, Fig 2] is configured to delete and optimize data in the memory card [24, Fig 2] using the selected first algorithm [Column 5, Lines 32 – 67; Column 6, Lines 1 – 16; The processor deletes and optimizes data on the memory card based on instructions in memory 31].
However, Parulski may not specifically disclose the limitation(s) of selecting a first algorithm among a plurality of algorithms for data deletion and optimization which are stored, the processor includes a remaining lifetime calculation circuit configured to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and an alarm circuit configured to be electrically connected to the remaining lifetime calculation circuit, the alarm circuit being configured to transmit a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Yasukawa discloses selecting a first algorithm among a plurality of algorithms for data deletion and optimization which are stored [203, Fig 1; 430, Fig 4D; S1003, Fig 5; S2007, Fig 6; Fig 9A; S4003, Fig 10; Paragraphs 0036 and 0066; The user selects from among multiple stored deletion and optimization algorithms to be executed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yasukawa in Parulski, because it allows for a user to determine how to delete data thereby making sure any old data is unreadable [Paragraphs 0002 – 0004 and 0066].
However, Parulski in view of Yasukawa may not specifically disclose the limitation(s) of the processor includes a remaining lifetime calculation circuit configured to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and an alarm circuit configured to be electrically connected to the remaining lifetime calculation circuit, the alarm circuit being configured to transmit a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Lee discloses a remaining lifetime calculation circuit [121, Figs 1 and 3] configured to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count [Paragraphs 0041 – 0042 and 0131; The monitoring information is based on SMART information which includes erase count wear] and an alarm circuit [127, Fig 3] configured to be electrically connected to the remaining lifetime calculation circuit [121, Figs 1 and 3], the alarm circuit [127, Fig 3] being configured to transmit a signal to the memory card via the first terminal [130, Fig 3; The flash interface sends signals from the controller to the flash memory device 130].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee in Parulski in view of Yasukawa, because it allows the system to monitor the health of the memory and alert a user when the memory health has fallen below a certain threshold [Paragraphs 0005 – 0006].
However, Parulski in view of Yasukawa in view of Lee may not specifically disclose the limitation(s) of the processor includes a remaining lifetime calculation circuit configured to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and circuitry that transmits a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Reimers discloses the processor [106, Fig 1; Paragraphs 0028 – 0030; The controller processes a routine making the controller a processor] includes a remaining lifetime calculation circuit configured to estimate a remaining lifetime [362, Fig 3] of the memory card [112 and 120, Fig 1] and circuitry that transmits a lock control signal to the memory card [112 and 120, Fig 1] when the estimated remaining lifetime reaches zero [363, Fig 3], wherein the lock control signal is configured to activate a lock setting circuit [112, Fig 1] in the memory card to render the memory card inaccessible [Fig 1; 365 and 369, Fig 3; Paragraph 0030; Claim 16; When the end of life is detected a signal is sent from the controller to remap addresses. When the last region is flagged and remapped the entire memory card is inaccessible due to the bad sections being unmapped and the last signal to remap the address is considered the lock control signal].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Reimers in Parulski in view of Yasukawa in view of Lee, because it adds a level of security to the card making sure no other system can accidentally access the card since the memory has reached its end of life.
Regarding claim 2, Parulski teaches the processor [20, Fig 2] is configured to perform:
a first operation for periodically checking whether the memory card that requires
the data deletion and optimization is connected to the first terminal [Figs 3, 8,10; Deleting an image or showing an image in memory shows there was a check performed to know the memory card is present and contains data that can be displayed or deleted. The check is performed periodically since the status window and display is based on the memory card being in the camera at the current time] and then the first algorithm is selected using the button [21, Fig 2; 54 and 56, Fig 3; Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; The buttons are used to delete data];
a second operation for displaying [50, Fig 3] the first algorithm [52f, Fig 3] and an operation state of the first algorithm [52f, Fig 3; Column 5, Lines 52 – 67; Column 6, Lines 1 – 4; Highlighting or not highlighting item 52f shows the operation state of the first algorithm is selected or not selected] and
a third operation for performing deletion and optimization of the data stored in the memory card according to the first algorithm [Column 5, Lines 52 – 67; Column 6, Lines 1 – 4; Data is deleted and optimized by deleting unwanted data to free up space on the memory card for more data].
Regarding claim 14, Parulski teaches a memory [31, Fig 2] storing an algorithm for data deletion and optimization [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; The deletion of data shows the use of memory to store the deletion algorithm which is also an optimization algorithm such that the memory is optimized by removing unwanted data] along with a firmware [32a, Fig 2] of the memory card reader [Fig 2].
Yasukawa discloses a memory storing the plurality of algorithms for the data deletion and optimization [203, Fig 1; Fig 4D; Paragraph 0025 and 0029; Multiple algorithms are stored in memory to allow the user to pick which delete algorithm to use].
Regarding claim 18, Lee discloses a circuit [120, Fig 1] in the memory card [110, Fig 1] configured to cause an external device accessing the memory card to output an error message, in response to the received lock control signal [S150, Fig 8; Paragraph 0072].
Reimers discloses the lock setting circuit [112, Fig 1] in the memory card [112 and 120, Fig 1].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parulski et al. (Pat 5,633,678) referred to as Parulski in view of Yasukawa (Pub. No.: US 2019/0187926) referred to as Yasukawa in view of Lee et al. (Pub. No.: US 2015/0339070) referred to as Lee in view of Reimers (Pub. No.: US 2017/0097781) referred to as Reimers as applied to claim 1 above, and further in view of Applicant’s Admitted Prior Art (Specification) referred to as AAPA.
Regarding claim 15, Parulski teaches a first algorithm for data deletion and optimization [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; One or more buttons are used to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card] which is stored in the memory card reader [31, Fig 2; Column 5, Lines 32 – 51; Item 31 stores instructions that are executed to operate the camera]
Yasukawa discloses selecting a first algorithm among a plurality of algorithms for data deletion and optimization which are stored [203, Fig 1; 430, Fig 4D; S1003, Fig 5; S2007, Fig 6; Fig 9A; S4003, Fig 10; Paragraphs 0036 and 0066; The user selects from among multiple stored deletion and optimization algorithms to be executed].
However, Parulski in view of Yasukawa in view of Yasukawa in view Lee of in view of Reimers may not specifically disclose the limitation(s) of the plurality of algorithms for the data deletion and optimization include U.S. DoD 5220.23-M(E), U.S. DoD 5220.23-M(ECE), German BCI/VSITR, Peter Gutmann, Bruce Schneier, Russian GOST R 50739-95, British HMG ISS(Baseline), British HMG ISS(Enhanced), NAVSO P-5239-26(MFM)/(RLL), Canadian RCMP TSSIT OPS-II US Army AR380-19, NATO Data Destruction Standard, MS Cipher, NSA erasure algorithm, Pfitzner, NCSC-TG-025, FSSI-5020, ISM 6.2.92, and NZSIT 402.
AAPA discloses the plurality of algorithms for the data deletion and optimization include U.S. DoD 5220.23-M(E), U.S. DoD 5220.23-M(ECE), German BCI/VSITR, Peter Gutmann, Bruce Schneier, Russian GOST R 50739-95, British HMG ISS(Baseline), British HMG ISS(Enhanced), NAVSO P-5239-26(MFM)/(RLL), Canadian RCMP TSSIT OPS-II US Army AR380-19, NATO Data Destruction Standard, MS Cipher, NSA erasure algorithm, Pfitzner, NCSC-TG-025, FSSI-5020, ISM 6.2.92, and NZSIT 402 [Specification, Paragraph 49; All the algorithms listed in the claim are listed in the specification as being conventional algorithms meaning they were known in the art at the time of the filling of the application making each algorithm admitted prior art by the applicant].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate AAPA in Parulski in view of Yasukawa in view of Yasukawa in view Lee of in view of Reimers, because all the algorithms are listed as being conventional in the art meaning one or ordinary skill in the art would know how to use each method and there would also be a high level of expected result of using the known algorithms.
Claim(s) 4 – 13, 16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parulski et al. (Pat 5,633,678) referred to as Parulski in view of Yasukawa (Pub. No.: US 2019/0187926) referred to as Yasukawa in view of Chrissy Montelli (How to format an SD card and erase all of its data) referred to as Montelli in view of Lee et al. (Pub. No.: US 2015/0339070) referred to as Lee in view of Reimers (Pub. No.: US 2017/0097781) referred to as Reimers.
Regarding claim 4, Parulski teaches a memory card reader [Fig 2; The camera reads a memory card making the camera a memory card reader] equipped with a self-data deletion and optimization function [52f, Fig 3; 63, Fig 4; 75, Fig 5; The camera deletes data and optimizes data by removing unwanted data], the memory card reader [Fig 2] comprising:
a first terminal [26, Fig 2] configured to be coupled to a memory card [24, Fig 2] and to perform interfacing with the memory card [Fig 2; Item 26 is the interface between the memory card and the camera];
an input circuit [29 and 30, Fig 2; 29 and 50, Fig 3; The display and associated buttons allow the user to provide input to the camera] configured to receive memory card commands deleting data on the memory card [24, Fig 2; Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; One or more buttons are used to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card] the input circuit [29 and 30, Fig 2; 29 and 50, Fig 3] being configured to receive a delete/optimize command for selecting a first algorithm for data deletion and optimization [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; One or more buttons are used to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card] which are stored in the memory card reader [31, Fig 2; Column 5, Lines 32 – 51; Item 31 stores instructions that are executed to operate the camera], and performing the data deletion and optimization on the memory card [24, Fig 2] based on the first algorithm [Column 5, Lines 32 – 67; Column 6, Lines 1 – 16; The processor deletes and optimizes data on the memory card based on instructions in memory 31];
a data deletion/optimization circuit [20, Fig 2] configured to be electrically connected to the input circuit [29 and 30, Fig 2; 29 and 50, Fig 3; The processor is directly or indirectly electrically connected to all other components of the camera] to receive the delete/optimize command [Column 5, Lines 32 – 67; Column 6, Lines 1 – 16; The processor deletes and optimizes data on the memory card based on user input through optimization of the memory by deleting unwanted data], the data deletion/optimization circuit [20, Fig 2] being configured to delete and optimize data stored in a data storage area [24a, Fig 2] of the memory card [24, Fig 2] using the selected algorithm according to the delete/optimize command received from the input circuit [29 and 30, Fig 2; 29 and 50, Fig 3; Column 5, Lines 52 – 67; Column 6, Lines 1 – 4; One or more buttons are used by a user to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card which are performed by the processor].
However, Parulski may not specifically disclose the limitation(s) of an input circuit configured to receive a format command for formatting the memory card, selecting a first algorithm among a plurality of algorithms for data deletion and optimization which are stored, and a format execution circuit configured to be electrically connected to the input circuit to receive the format command, the format execution circuit being configured to execute formatting for the memory card according to the format command received from the input circuit, a remaining lifetime calculation circuit to be electrically connected to the data deletion/optimization circuit and to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and an alarm circuit configured to be electrically connected to the remaining lifetime calculation circuit, the alarm circuit being configured to transmit a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Yasukawa discloses selecting a first algorithm among a plurality of algorithms for data deletion and optimization which are stored [203, Fig 1; 430, Fig 4D; S1003, Fig 5; S2007, Fig 6; Fig 9A; S4003, Fig 10; Paragraphs 0036 and 0066; The user selects from among multiple stored deletion and optimization algorithms to be executed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yasukawa in Parulski, because it allows for a user to determine how to delete data thereby making sure any old data is unreadable [Paragraphs 0002 – 0004 and 0066].
However, Parulski in view of Yasukawa may not specifically disclose the limitation(s) of an input circuit configured to receive a format command for formatting the memory card and a format execution circuit configured to be electrically connected to the input circuit to receive the format command, the format execution circuit being configured to execute formatting for the memory card according to the format command received from the input circuit, a remaining lifetime calculation circuit to be electrically connected to the data deletion/optimization circuit and to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and an alarm circuit configured to be electrically connected to the remaining lifetime calculation circuit, the alarm circuit being configured to transmit a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Montelli discloses an input circuit configured to receive a format command for formatting the memory card and a format execution circuit configured to be electrically connected to the input circuit to receive the format command, the format execution circuit being configured to execute formatting for the memory card according to the format command received from the input circuit [Pages 7 – 8; How to format an SD card using a DSLR camera; The display on the camera provides a format command option the user selects resulting in the processor of the camera formatting the memory card in the camera. The circuit that performs the formatting is electrically connected to the input circuit to receive the input to perform the format operation].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Montelli in Parulski in view of Yasukawa, because it allows a user to erase all data, including hidden data, on a memory card and allows the configuration of the memory card to be changed if needed [Page 2, Lines 1 – 6].
However, Parulski in view of Yasukawa in view of Montelli may not specifically disclose the limitation(s) of a remaining lifetime calculation circuit to be electrically connected to the data deletion/optimization circuit and to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and an alarm circuit configured to be electrically connected to the remaining lifetime calculation circuit, the alarm circuit being configured to transmit a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Lee discloses a remaining lifetime calculation circuit [121, Figs 1 and 3] connected to the data deletion/optimization circuit [Paragraphs 0041 – 0042; The lifetime calculation is based on an erase/delete count showing the lifetime calculation circuit is connected to the circuit that deletes data and records the number of times data was deleted] configured to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count [Paragraphs 0041 – 0042 and 0131; The monitoring information is based on SMART information which includes erase count wear] and an alarm circuit [127, Fig 3] configured to be electrically connected to the remaining lifetime calculation circuit [121, Figs 1 and 3], the alarm circuit [127, Fig 3] being configured to transmit a signal to the memory card via the first terminal [130, Fig 3; The flash interface sends signals from the controller to the flash memory device 130].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee in Parulski in view of Yasukawa in view of Montelli, because it allows the system to monitor the health of the memory and alert a user when the memory health has fallen below a certain threshold [Paragraphs 0005 – 0006].
However, Parulski in view of Yasukawa in view of Montelli in view of Lee may not specifically disclose the limitation(s) of a remaining lifetime calculation circuit configured to estimate a remaining lifetime of the memory card based on a deletion/optimization execution count and circuitry that transmits a lock control signal to the memory card via the first terminal when the estimated remaining lifetime reaches zero, wherein the lock control signal is configured to activate a lock setting circuit in the memory card to render the memory card inaccessible.
Reimers discloses the processor [106, Fig 1; Paragraphs 0028 – 0030; The controller processes a routine making the controller a processor] includes a remaining lifetime calculation circuit configured to estimate a remaining lifetime [362, Fig 3] of the memory card [112 and 120, Fig 1] and circuitry that transmits a lock control signal to the memory card [112 and 120, Fig 1] when the estimated remaining lifetime reaches zero [363, Fig 3], wherein the lock control signal is configured to activate a lock setting circuit [112, Fig 1] in the memory card [112 and 120, Fig 1] to render the memory card inaccessible [Fig 1; 365 and 369, Fig 3; Paragraph 0030; Claim 16; When the end of life is detected a signal is sent from the controller to remap addresses. When the last region is flagged and remapped the entire memory card is inaccessible due to the bad sections being unmapped and the last signal to remap the address is considered the lock control signal].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Reimers in Parulski in view of Yasukawa in view of Montelli in view of Lee, because it adds a level of security to the card making sure no other system can accidentally access the card since the memory has reached its end of life.
Regarding claim 5, Parulski teaches a second terminal configured to be coupled to a host computer and to perform interfacing with the host computer [Fig 2; 64, Fig 4; 64, Fig 5; Column 6, Lines 60 – 67; Column 7, Lines 1 – 7; The camera is connected to a computer showing a host interface to enable the connection],
the data deletion/optimization circuit [20, Fig 2] is configured to receive the delete/optimize command [Column 5, Lines 32 – 67; Column 6, Lines 1 – 16] and to delete and optimize the data stored in the data storage area according to the received delete/optimize command [29 and 30, Fig 2; 29 and 50, Fig 3; Column 5, Lines 52 – 67; Column 6, Lines 1 – 4; One or more buttons are used by a user to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card which are performed by the processor].
Montelli discloses wherein the format execution circuit is configured to receive the format command from the host computer through an interface with the second terminal and to execute the formatting for the memory card according to the received format command, and the data deletion/optimization circuit is configured to receive the delete/optimize command from the host computer through an interface with the second terminal [Pages 2 – 3, How to format an SD card on a Windows PC; The USB reader is equivalent to a digital camera since both read memory cards. The user uses a screen to select the format option which formats the memory card. The format operation is also a delete and optimization operation since the format process deletes data and optimizes the storage for a specific format].
Regarding claim 6, Parulski teaches a memory card interface circuit [26, Fig 2] configured to be electrically connected to the second terminal [64, Fig 4; 64, Fig 5; Column 6, Lines 60 – 67; Column 7, Lines 1 – 7; The camera and computer are connected though the connection to the computer and the interface of the memory card interface allowing data to transfer between the computer and memory card in the camera].
Montelli discloses circuits and terminals to format the memory card [Pages 2 – 8; How to format an SD card on Windows PC; How to format an SD card using a DSLR camera; The USB reader in the Windows process is equivalent to a digital camera since both read memory cards. This shows there are circuits and terminals in the camera that receives and stores the format information on the memory card in the formatting process. The display on the camera provides a format command option the user selects resulting in the processor of the camera formatting the memory card in the camera] .
Lee discloses a circuit [120, Fig 1] configured to, when the memory card is formed of a non-volatile memory express (NVMe) memory [Paragraph 0037; The NVMe protocol being used shows a NVMe memory is used], receive self-monitoring, analysis and reporting technology (S.M.A.R.T) information [Paragraph 0131; The monitoring information is based on SMART information] related to data deletion/writing from the host computer through the second terminal, and to store the received S.M.A.R.T information [Figs 8, 12, and 14; The controller receives and stores SMART information based on a command from the host], wherein the remaining lifetime calculation circuit [120, Fig 1] is configured to be electrically connected to the memory card information storage circuit [Fig 1; All devices in figure 1 are electrically connected to each other] and to calculate the remaining lifetime of the memory card using the S.M.A.R.T information [Paragraph 0131; The monitoring information is based on SMART information] stored in the memory card information storage circuit [120, Fig 1; S140, Fig 8; S240, Fig 12; S330, Fig 14], and alarm circuit [120, Fig 1] is configured to generate an alarm for a replacement time of the memory card using the remaining lifetime of the memory card which is automatically calculated by the remaining lifetime calculation circuit and to output the generated alarm through a display [S150, Fig 8; S250, Fig 12; S340, Fig 14; 2500, Fig 18; Paragraphs 0041 – 0044 and 0124; The display is used to display information to the user from the system such as the end of life warning signal sent to the user].
Regarding claim 7, Parulski teaches a memory card interface circuit [26, Fig 2] configured to be electrically connected to the second terminal [64, Fig 4; 64, Fig 5; Column 6, Lines 60 – 67; Column 7, Lines 1 – 7; The camera and computer are connected though the connection to the computer and the interface of the memory card interface allowing data to transfer between the computer and memory card in the camera].
Montelli discloses circuits and interfaces to format the memory card [Pages 7 – 8; How to format an SD card using a DSLR camera; The display on the camera provides a format command option the user selects resulting in the processor of the camera formatting the memory card in the camera].
Lee discloses a data deletion/optimization count circuit [120, Fig 1] configured to be electrically connected to the data/deletion circuit and to count a number of times the data deletion and optimization is performed by the data deletion/optimization circuit [Paragraphs 0035 and 0041 – 0042; The controller counts the number of erase operations and performs the erase operations showing the counting and erasing circuits are electrically connected since they are both in the controller and the counting circuit knows how many times the erasing circuit performs an erase].
Regarding claim 8, Parulski teaches a memory card interface circuit [26, Fig 2] configured to be electrically connected to the second terminal [64, Fig 4; 64, Fig 5; Column 6, Lines 60 – 67; Column 7, Lines 1 – 7; The camera and computer are connected though the connection to the computer and the interface of the memory card interface allowing data to transfer between the computer and memory card in the camera] and performing deletion and optimization operations [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; One or more buttons are used to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card].
Montelli discloses the format execution circuit is configured to execute the formatting for the memory card by separately specifying within the memory card, the data storage area for storing conventional data, and a memory card information area for storing memory card information [Pages 2 – 8; Formatting a memory card sets up areas of the memory card to store data and also store information the defines the format of the memory. The specific bit locations of the data and information are separate since a specific bit location can only hold one unit of data at a time].
Lee discloses a memory card deletion/optimization count storage area for storing a number of times the data deletion and optimization has been performed on the memory card [110, Fig 1; Paragraphs 0035 and 0041 – 0042; 110 is considered a memory card and the specific bit locations of where the erase count information is stored is separate from any other bit locations where other information may be stored].
Regarding claim 9, Parulski teaches a memory card interface circuit configured to perform interfacing [26, Fig 2] with a memory card [24, Fig 2] and attaching a card reader in the form of a digital camera to a host through the second terminal [Fig 2; 64, Fig 4; 64, Fig 5; Column 6, Lines 60 – 67; Column 7, Lines 1 – 7; The camera is connected to a computer showing a host interface to enable the connection].
Montelli discloses the memory card information storage circuit is configured to receive memory card information from the host computer through the interface with the second terminal and to store the memory card information, and further comprising a memory card information automatic storage control circuit electrically connected to the second terminal, the memory card information automatic storage control circuit being configured to receive the memory card information of the memory card from the host computer through the interface with the second terminal and to automatically store the received memory card information in a memory card information storage area of the memory card [Pages 2 – 8; When a memory card is formatted a system is able to read the format information of the memory card to know how to access the memory card. Formatting a memory card through Windows shows the use of modules to receive the format information, such as NTFS or FAT32, and store that information in the memory and perform the formatting based on that information. All circuits in the camera are electrically connected to each other since they are all part of the camera].
Regarding claim 10, Parulski teaches the first terminal [26, Fig 2] configured to perform interfacing with a memory card [24, Fig 2].
Montelli discloses the display is configured to display the memory card information [Pages 2 – 7; The Windows and Mac methods show the display displaying the memory card information].
Lee discloses the display is configured to displaying the remaining lifetime of the memory card [S150, Fig 8; S250, Fig 12; S340, Fig 14; 2500, Fig 18; Paragraphs 0041 – 0044 and 0124; The end of lifetime warning is an indication of the remaining lifetime being less than a threshold].
Regarding claim 11, Parulski teaches a memory card automatic recognition circuit configured to be electronically connected to the first terminal [26, Fig 2] and to automatically recognize the memory card information stored in the memory card information storage area, through an interface with the first terminal [26, Fig 2] and a memory card automatic identification circuit configured to be electronically connected to the memory card automatic recognition circuit and to search the memory card information stored in the memory card information storage circuit for the memory card information automatically recognized by the memory card automatic recognition circuit to automatically identify the memory card [Fig 2; 63, Fig 4; The storing of data shows the use of one or more circuits in the camera that are able to search and recognize the information of the memory card through the interface the memory card is connected to in the camera to be able to store data in the memory card in an appropriate manner according to the information indicating a format of the memory card. All the circuitry of the camera is electronically connected together].
Lee discloses a circuit determining a number of times the data deletion and optimization has been performed on the memory card [Paragraphs 0035 and 0041 – 0042].
Regarding claim 12, Parulski teaches Parulski teaches the first terminal [26, Fig 2] configured to perform interfacing with a memory card [24, Fig 2].
Lee teaches the remaining lifetime automatic circuit is configured to add a number of times the data deletion and optimization is performed by the by the data deletion/optimization circuit, that is counted by a data deletion/optimization count circuit to the number of times the data deletion and optimization has been performed on the memory card that is automatically recognized by the memory card automatic recognition circuit to calculate a final number of times of the data deletion and optimization, automatically calculate the remaining lifetime of the memory card according to the calculated final number of times referring to a storage method stored in a memory card information storage circuit, and output the calculated remaining lifetime of the memory card through the display [Figs 8, 12, and 14; One or more circuits are used to recognize old erase counts, add new erase counts to the old erase counts, and then compare the result of the adding to a threshold to know the lifetime of the memory device compared to a threshold value. This is all based on a storage method used for the memory card allowing data to be stored on the memory].
Regarding claim 13, Parulski teaches the first terminal [26, Fig 2] configured to perform interfacing with a memory card [24, Fig 2] and storing information in the memory card through the first terminal [26, Fig 2].
Lee discloses a memory card deletion/optimization count storage circuit configured to be electronically connected to the remaining lifetime calculation circuit and to store the final number of times that is calculated by the remaining lifetime calculation circuit and a memory card deletion/optimization count automatic storage control circuit configured to be connected to the memory card deletion/optimization count storage circuit and to control the final number of times that is stored in the memory card deletion/optimization count storage circuit to be automatically stored in a memory card deletion/optimization count storage area of the memory card [110, fig 1; Figs 8, 12, and 14; The controller and nonvolatile memory device are both part of 110 which is equivalent to a memory card. The system 110 controls a count of the number of delete/optimization operations. The area where the count information is stored in 110 is a memory card deletion/optimization count area of 110. The units or devices in 110 that perform the counting and managing of the counts are considered circuits and all the circuits in 100 in figure 1 are electronically connected to each other directly or indirectly].
Regarding claim 16, Parulski teaches a memory [31, Fig 2] storing an algorithm for data deletion and optimization [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; The deletion of data shows the use of memory to store the deletion algorithm which is also an optimization algorithm such that the memory is optimized by removing unwanted data] along with a firmware [32a, Fig 2] of the memory card reader [Fig 2].
Yasukawa discloses a memory storing the plurality of algorithms for the data deletion and optimization [203, Fig 1; Fig 4D; Paragraph 0025 and 0029; Multiple algorithms are stored in memory to allow the user to pick which delete algorithm to use].
Regarding claim 19, Lee discloses a circuit [120, Fig 1] in the memory card [110, Fig 1] configured to cause an external device accessing the memory card to output an error message, in response to the received lock control signal [S150, Fig 8; Paragraph 0072].
Reimers discloses the lock setting circuit [112, Fig 1] in the memory card [112 and 120, Fig 1].
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parulski et al. (Pat 5,633,678) referred to as Parulski in view of Yasukawa (Pub. No.: US 2019/0187926) referred to as Yasukawa in view of Chrissy Montelli (How to format an SD card and erase all of its data) referred to as Montelli in view of Lee et al. (Pub. No.: US 2015/0339070) referred to as Lee in view of Reimers (Pub. No.: US 2017/0097781) referred to as Reimers as applied to claim 4 above, and further in view of Applicant’s Admitted Prior Art (Specification) referred to as AAPA.
Regarding claim 17, Parulski teaches a first algorithm for data deletion and optimization [Column 5, Lines 52 – 67; Column 6, Lines 1 – 16; One or more buttons are used to select an algorithm such as deleting data which also optimizes the data by removing unwanted data thus freeing up space on the memory card] which is stored in the memory card reader [31, Fig 2; Column 5, Lines 32 – 51; Item 31 stores instructions that are executed to operate the camera]
Yasukawa discloses selecting a first algorithm among a plurality of algorithms for data deletion and optimization which are stored [203, Fig 1; 430, Fig 4D; S1003, Fig 5; S2007, Fig 6; Fig 9A; S4003, Fig 10; Paragraphs 0036 and 0066; The user selects from among multiple stored deletion and optimization algorithms to be executed].
However, Parulski in view of Yasukawa in view of Montelli in view Lee of in view of Reimers may not specifically disclose the limitation(s) of the plurality of algorithms for the data deletion and optimization include U.S. DoD 5220.23-M(E), U.S. DoD 5220.23-M(ECE), German BCI/VSITR, Peter Gutmann, Bruce Schneier, Russian GOST R 50739-95, British HMG ISS(Baseline), British HMG ISS(Enhanced), NAVSO P-5239-26(MFM)/(RLL), Canadian RCMP TSSIT OPS-II US Army AR380-19, NATO Data Destruction Standard, MS Cipher, NSA erasure algorithm, Pfitzner, NCSC-TG-025, FSSI-5020, ISM 6.2.92, and NZSIT 402.
AAPA discloses the plurality of algorithms for the data deletion and optimization include U.S. DoD 5220.23-M(E), U.S. DoD 5220.23-M(ECE), German BCI/VSITR, Peter Gutmann, Bruce Schneier, Russian GOST R 50739-95, British HMG ISS(Baseline), British HMG ISS(Enhanced), NAVSO P-5239-26(MFM)/(RLL), Canadian RCMP TSSIT OPS-II US Army AR380-19, NATO Data Destruction Standard, MS Cipher, NSA erasure algorithm, Pfitzner, NCSC-TG-025, FSSI-5020, ISM 6.2.92, and NZSIT 402 [Specification, Paragraph 49; All the algorithms listed in the claim are listed in the specification as being conventional algorithms meaning they were known in the art at the time of the filling of the application make each algorithm admitted prior art by the applicant].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate AAPA in Parulski in view of Yasukawa in view of Montelli in view Lee of in view of Reimers, because all the algorithms are listed as being conventional in the art meaning one or ordinary skill in the art would know how to use each method and there would also be a high level of expected result of using the known algorithms.
Response to Arguments
Applicant's arguments filed 04/28/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 12 – 17 that the claims are in condition for allowance since the previous prior art fails to teach the newly amended limitation in the claims. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution.
Conclusion
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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