DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/6/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: in paragraphs [0029] and [0031] “photoelectric conversion layer 25” should be –photoelectric conversion layer 24--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moriwaki (WO 2020/202902, using US 2022/0208857 as the English translation).
As to claims 1 and 13, Moriwaki teaches a photodetector (imaging element) comprising a plurality of pixels each including one or a plurality of photoelectric conversion elements (10, [0126]), the photoelectric conversion element (10, fig. 1) comprising:
a first electrode (21) and a second electrode (24) disposed side by side with each other ([0177]);
a third electrode (22) disposed to be opposed to the first electrode (21) and the second electrode (24, [0177]);
a photoelectric conversion layer (23A) provided between the first electrode (21) and the third electrode (24) and between the second electrode (22) and the third electrode (24, [0164]); and
a semiconductor layer (23B) provided between the first electrode (21) and the photoelectric conversion layer (23A) and between the second electrode (24) and the photoelectric conversion layer (23A, [0162]),
the semiconductor layer (23B) including a first layer (23C) and a second layer (23D) stacked in order from a side of the first electrode (21) and the second electrode (24, [0162]),
the first layer (23C) having a thickness smaller than a thickness of the second layer (23D, table 1), the thickness of the first layer being 3 nm or more and 5 nm or less ([0519] and claim 1, 3nm is anticipated, as it is claimed.).
As to claim 9, Moriwaki further teaches an insulating layer (82) provided between the first electrode (21) and the semiconductor layer (23B) and between the second electrode (24) and the semiconductor layer (23B, fig. 1),
the insulating layer having an opening (85) above the first electrode, and the second electrode and the semiconductor layer are electrically coupled to each other via the opening ([0313]).
As to claim 11, Moriwaki further teaches the first electrode (21) and the second electrode (24) are disposed on a side opposite to a light incident surface with respect to the photoelectric conversion layer (fig. 1, light enters through the microlens 14).
As to claim 12, Moriwaki further teaches respective voltages are applied individually to the first electrode and the second electrode ([0426]).
As to claim 14, Moriwaki further teaches the photoelectric conversion element further includes one or a plurality of photoelectric conversion regions that performs photoelectric conversion of a wavelength region different from the one or the plurality of photoelectric conversion elements ([0268] – [0280]).
As to claim 15, Moriwaki further teaches the one or the plurality of photoelectric conversion regions is formed to be embedded in a semiconductor substrate, and the one or the plurality of photoelectric conversion sections is disposed on a side of a light incident surface of the semiconductor substrate ([0268] – [0280]).
As to claim 16, Moriwaki further teaches a multilayer wiring layer (62) is formed on a surface of the semiconductor substrate on a side opposite to the light incident surface ([0318]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Moriwaki.
As to claims 2 and 4-6, Moriwaki does not explicitly teach the ratios and properties claimed. However, determining these ratios and crystallinities would have been obvious so as to modify oxide semiconductor layer properties to mee the required design parameters.
Allowable Subject Matter
Claims 3, 7, 8, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 3, Moriwaki explicitly teaches the first and second layers are identical in composition ([0167]), thus they cannot have different indium compositions.
As to claims 7 and 8, Moriwaki does not teach a third oxide semiconductor layer.
As to claim 10, Moriwaki does not teach a protective layer between the photoelectric conversion layer and the semiconductor layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
9/6/26
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