Prosecution Insights
Last updated: August 17, 2026
Application No. 18/844,984

CIRCUIT BOARD AND DISPLAY DEVICE HAVING SAME

Non-Final OA §103
Filed
Sep 09, 2024
Priority
Jun 14, 2022 — CN 202210672765.4 +1 more
Examiner
NG, SHERMAN
Art Unit
Tech Center
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
410 granted / 541 resolved
+15.8% vs TC avg
Strong +17% interview lift
Without
With
+16.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
3 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
60.7%
+20.7% vs TC avg
§102
31.4%
-8.6% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application No. 18/844,984 filed on 03/05/2025. Information Disclosure Statement The information disclosure statement filed 03/05/2025 has been submitted for consideration by the Office. It has been placed in the application file and the information referred to therein has been considered. Claim Objections Claims 14-20 are objected to because of the following informalities: Claims 14-20 recite “A display device, comprising the display circuit…” It should be amended to recite “A display device, comprising the printed circuit board…” since no antecedent basis for “display circuit” is established in claims 1-7; respectively. Appropriate correction is required. Allowable Subject Matter Claims 3-8, 10-13, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 9, 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over LIM et al. (US 2016/0353572) in view of Kim et al. (US 6,631,838). Regarding claim 1, Lim discloses a circuit board (See Fig. 21), comprising: a circuit board body [811], wherein a part mounting face [top surface of 811] is formed on one side of the circuit board body [811]; a base face [bottom surface of 811] is formed on the other side of the circuit board body [811] opposite to the part mounting face [top surface of 811]; the part mounting face [top surface of 811] is provided with a heat dissipation bonding pad [812]; the circuit board body [811] is provided with heat dissipation holes [See paragraph 0097: via holes of the insulating layer 811] penetrating from the base face [bottom surface of 811] to the heat dissipation bonding pad [812]; the base face [bottom surface of 811] is provided with a bottom solder mask [814]; the bottom solder mask [814] flows into the heat dissipation holes [See paragraph 0097: via holes of the insulating layer 811] such that the heat dissipation holes [See paragraph 0097: via holes of the insulating layer 811] are formed into semi-plug holes [See Fig. 21: portion of solder mask 814 that is inserted into the via holes of the insulating layer 811]. Lim does not disclose reinforced solder masks are provided outside the bottom solder mask; and the reinforced solder masks cover the semi-plug holes in a sealing manner. Kim teaches (in Fig. 3F) reinforced solder masks [37] are provided outside the bottom solder mask [35] (See Fig. 3F: In an upside-down view, reinforced solder masks 37 are provided outside the bottom solder mask); and the reinforced solder masks [37] cover the semi-plug holes [35] in a sealing manner. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board of Lim to have reinforced solder masks are provided outside the bottom solder mask; and the reinforced solder masks cover the semi-plug holes in a sealing manner, as taught by Kim, in order to provide a printed circuit board in which an air space does not result in a portion of a printed circuit board collapsing, thereby improving the adhesion between the printed circuit board and the solder resist (as taught by Kim in Column 2, lines 26-30). Regarding claim 2, Lim, as applied to claim 1, further discloses (in Fig. 21) wherein a semi-plug hole conduction portion [813] is provided at a semi-plug hole [See paragraph 0097: via holes of the insulating layer 811]; the semi-plug hole conduction portion [813] comprises a conduction portion body [See Fig. 21 tagged below for labeling of conduction portion body] located in the semi-plug hole [See paragraph 0097: via holes of the insulating layer 811] and a bottom bonding pad [See Fig. 21 tagged below for labeling of bottom bonding pad] located on the base face [bottom surface of 811]; the conduction portion body [See Fig. 21 tagged below for labeling of conduction portion body] is configured to be electrically connected to the heat dissipation bonding pad [812]; the bottom bonding pad [See Fig. 21 tagged below for labeling of bottom bonding pad] is configured to be electrically connected to the conduction portion body [See Fig. 21 tagged below for labeling of conduction portion body]; the bottom solder mask [814] covers the bottom bonding pad [See Fig. 21 tagged below for labeling of bottom bonding pad]. PNG media_image1.png 1091 957 media_image1.png Greyscale Lim does not disclose the reinforced solder masks cover the bottom bonding pad from outside the bottom solder mask in a sealing manner. Kim teaches (in Fig. 3F) reinforced solder masks [37] cover the bottom bonding pad [34] from outside the bottom solder mask [35] in a sealing manner [See Fig. 3F: In an upside-down view, reinforced solder masks 37 cover the bottom bonding pad 34 from outside the bottom solder mask 35 in a sealing manner]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board of Lim to have the reinforced solder masks cover the bottom bonding pad from outside the bottom solder mask in a sealing manner, as taught by Kim, in order to provide a printed circuit board in which an air space does not result in a portion of a printed circuit board collapsing, thereby improving the adhesion between the printed circuit board and the solder resist (as taught by Kim in Column 2, lines 26-30). Regarding claim 9, Lim, as applied to claim 1, further discloses (in Fig. 21) wherein a quantity of the semi-plug holes [See Fig. 21: portion of solder mask 814 that is inserted into the via holes of the insulating layer 811] corresponding to a single heat dissipation bonding pad [812] is multiple. Regarding claim 14, Lim and Kim, as applied to claim 1, do not disclose a display device, comprising the printed circuit board according to claim 1. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board of Lim to include a display device, comprising the printed circuit board, in order to provide a display device having good heat dissipation. Regarding claim 15, Lim and Kim, as applied to claim 2, do not disclose a display device, comprising the printed circuit board according to claim 2. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board of Lim to include a display device, comprising the printed circuit board, in order to provide a display device having good heat dissipation. Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHERMAN NG whose telephone number is (571)270-3131. The examiner can normally be reached Mon-Fri 10AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHERMAN NG/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 09, 2024
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
92%
With Interview (+16.6%)
2y 4m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allowance rate.

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