Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1-4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: a node “P” in Figs. 5, 6, 8, and 9.
The drawings are also objected to because the Fig. 5 and Fig. 6 are identical. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is objected to because of the following informalities: In line 5, it appears that the recitation, “connected to the output terminal” should be deleted. Appropriate correction is required.
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baehring (US 4,587,447, hereinafter referred to as Baehring).
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Regarding claim 1, Baehring discloses an inverter (see annotated Fig. 2 above) comprising:
a first load transistor (T5) having a gate electrode (G) and a drain electrode (D) that are connected to a power voltage (VDD) terminal (VDD);
a second load transistor (T7) having a gate electrode (G) and a drain electrode (D) that are connected to a source electrode (S) of the first load transistor (T5), the second load transistor (T7) having a source electrode (S) connected to an output terminal (OUT or A via T4);
a driving transistor (T6) having a drain electrode (D) connected to the source electrode (S) of the second load transistor (T7) such that the output terminal (OUT or A via T4) is formed, the driving transistor (T6) having a gate electrode (G) connected to an input (Vin) terminal (E via R) and having a source electrode (S) connected to a ground (GND) terminal (VSS via T1); and
a control transistor (T2) having a drain electrode (D) connected to the source electrode (S) of the first load transistor (T5 via C), having a gate electrode (G) connected to the input (Vin) terminal (E via R), and having a source electrode (S) connected to the ground (GND) terminal (VSS via T1).
Allowable Subject Matter
Claims 3 and 4 are allowed.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the best prior art of record, Baehring, taken alone or in combination of other references, does not teach or fairly suggest an inverter comprising, among other things, when the gate electrode of the control transistor is turned on… so that a voltage of a node (P) to which the drain electrode of the second load transistor and the source electrode of the first load transistor are connected becomes 0V, as set forth in the claim 2.
The best prior art of record, Song, discloses a bootstrap inverter (Figs. 1-4) comprising: a first load transistor (13, 23), a second load transistor (15, 25), a bootstrap transistor (11, 21), a driving transistor (17, 29), as set forth in the claim 3.
However, Song, taken alone or in combination of other references, does not teach or fairly suggest a bootstrap inverter comprising, among other things, a control transistor having a drain electrode connected to the source electrode of the first load transistor, as set forth in the claim 3. Dependent claim 4 is allowed on its respective dependency from the independent claim 3. Hence, the Claims 3 and 4 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Callahan (US 3,927,334) discloses a MOSFET bootstrap buffer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 5712728048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D CHANG/Primary Examiner, Art Unit 2844