DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of information disclosure statement filed 3 March 2025.
Response to Amendment
Acknowledgment is made of applicant’s preliminary amendment in which the following is noted: claims 3, 5, 7, 11, 13, 17, 19, 22, 24, 25, 29, 32, 36, and 37 are amended and claims 4, 6, 8-10, 12, 15-16, 21, 23, 26-27,30-31, and 33-35 are cancelled. Claims 1 – 3, 5, 7, 11, 13 – 14, 17 – 20, 22, 24 – 25, 28 – 29, 32, and 36 – 37 are currently pending and an Office action on the merits follows.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al; (Publication number: US 2021/0166597 A1), hereafter Feng, in view of Yoshihisa Takahashi (Publication number: US 2019/0311689 A1), hereafter Takahashi.
Regarding claim 1:
Feng discloses a display substrate (Feng Figure 12 and [0003] TFT-based LCD or AMOLED including gate drive on array (GOA))), comprising:
a first region and a second region (Feng Figure 12 first region corresponds to area of gate drive circuit 1210 and second region corresponds to display area of AMOELD or TFT-LCD display), wherein the first region is provided with pixel drive circuits arranged in an array (Feng [0003] inherent to AMOLED or TFT-based LCD), the second region is provided with a gate drive circuit configured to provide a drive signal to the pixel drive circuits (Feng Figure 12 and [0003] gate driving circuit configured as GOA type), the gate drive circuit comprises:
a plurality of shift registers (Feng Figure 10 see cascaded shift registers SR1, SR2, SR3, SR4; [0124])), at least one stage of shift register comprises:
a pre-circuit (Feng Figure 3 210-1) and a drive output circuit (Feng Figure 3 220-1), the pre-circuit is electrically connected to a signal input terminal (Feng Figure 3 terminal IN1 connected to circuit 210-1), a rest signal terminal and a cascaded output signal terminal respectively (Feng Figure 3 – sub-circuit 210-1 connected to terminal RST1 and output sub-circuit 220-1 via node PU), the drive output circuit is electrically connected to N drive signal output terminals respectively (Feng Figure 3 220-1 connected to cascaded output sub-circuits 220-N), a signal input terminal of at least one stage of at least one stage of shift register is electrically connected to a cascaded output signal terminal of at least one stage of shift register (Feng Figure 3 – terminal IN1 connected to terminal OUT1 of output sub-circuit 220-1 via node PU), a rest signal terminal of at least one stage of shift register is electrically connected to a cascaded output signal terminal of at least one stage of shift register (Feng Figure 3 – terminal RST1 of 250-1 connected to OUT1 of output sub-circuit 210-1 via nodes PU or VSS), the drive output circuit comprises:
n drive output sub-circuits (Feng Figure 3 – output sub-circuits 220-1 to 220-N), an n-th drive output sub-circuit is electrically connected to an n-th drive signal output terminal (Feng Figure 3 OUTN; [0051]), in at least one display frame, a start time of a drive signal output from a N-th drive signal output terminal is later than a start time of a drive signal output from at least one of a first drive signal output terminal to an (N-1)-th drive signal output terminal, N>2, 1 ≤ n≤ N (Feng Figure 8 – implicitly disclosed by timing diagram of shift register with sequential output of output terminal OUT1 and OUT2 during the display phase).
Feng does not disclose an area of the N-th drive output sub-circuit is larger than an area of at least one of a first drive output sub-circuit to an (N-1)-th drive output sub-circuit.
However, Takahashi discloses a drive circuit and display apparatus. More particularly, Takahashi discloses an area of the N-th drive output sub-circuit is larger than an area of at least one of a first drive output sub-circuit to an (N-1)-th drive output sub-circuit (Takahashi Figure 7 – illustrates channel width which are increased along the branch points of the shift registers SR1 – SRi)
It would have been obvious to modify Feng wherein an area of the N-th drive output sub-circuit is larger than an area of at least one of a first drive output sub-circuit to an (N-1)-th drive output sub-circuit, as claimed. Those skilled in the art would appreciate making the waveforms of the driving signals uniform (Takahashi [0010]).
Regarding claim 37:
Feng (in view of Takahashi) discloses a display apparatus, comprising the display substrate according to claim 1 (Feng Figure 12 and [0003] TFT-based LCD or AMOLED including gate drive on array (GOA)).
Claim(s) 2, 3, and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al; (Publication number: US 2021/0166597 A1), hereafter Feng, in view of Yoshihisa Takahashi (Publication number: US 2019/0311689 A1), hereafter Takahashi, in view of Zhu et al; (Publication number: US 2022/0344425 A1), hereafter Zhu.
Regarding claim 2:
Feng (in view of Takahashi) discloses at least one drive sub-circuit comprises: an output transistor (Feng Figure 4 T21), a noise reduction transistor (Feng Figure 4 T31) and an output capacitor (Feng Figure 4 C1), a transistor comprises: an active pattern, a gate electrode, a first electrode and a second electrode, and the output capacitor comprises: a first plate and a second plate (a gate/first/second electrode and active pattern are inherent to a transistor; similarly a first plate and second plate are inherent to a capacitor).
Feng (in view of Takahashi) does not disclose the display substrate according to claim 1, comprising: a base substrate and drive structure layer arranged on the base substrate, the gate dive circuit and the pixel drive circuits are located on the drive structure layer, the drive structure layer comprises: a semiconductor layer, a first conductive layer and a second conductive layer stacked sequentially on the base substrate; the semiconductor layer at least comprises: an active pattern of an output transistor and an active pattern of the noise reduction transistor is located on at least one drive output sub-circuit; a first conductive layer at least comprises: a second plate of an output capacitor located on at least one drive output sub-circuit; and a second conductive layer comprises: a first plate of an output capacitor, a gate electrode; a first electrode and a second of an output transistor, and a gate electrode, a first electrode and a second electrode of a noise reduction transistor located on at least one drive output sub-circuit.
However, Zhu discloses a display panel and display apparatus. More particularly, Zhu discloses a base substrate (Zhu Figure 3 base substrate101) and drive structure layer arranged on the base substrate, the gate dive circuit and the pixel drive circuits are located on the drive structure layer (Zhu Figure 3B – layer containing elements N2G and N2D of gate driver), the drive structure layer comprises:
a semiconductor layer (Zhu Figure polysilicon 102), a first conductive layer and a second conductive layer stacked sequentially on the base substrate (Zhu Figure 3B 302, 301);
the semiconductor layer at least comprises: an active pattern of an output transistor and an active pattern of the noise reduction transistor is located on at least one drive output sub-circuit (Zhu Figure 3B N4a and N2A; [0140]);
a first conductive layer at least comprises: a second plate of an output capacitor located on at least one drive output sub-circuit (Zhu Figure 2C storage sub-circuit 113 comprises a second plate 141); and
a second conductive layer comprises: a first plate of an output capacitor, a gate electrode (Zhu Figure 2C storage sub-circuit comprises a first plate 142; Figure 3B N2G) a first electrode and a second of an output transistor, and a gate electrode, a first electrode and a second electrode of a noise reduction transistor located on at least one drive output sub-circuit (Zhu Figure 3B N2D, N2G, N2S; N4S/N4D located on same layer).
It would have been obvious to further modify Feng (in view of Takashi) to include a base substrate and drive structure layer arranged on the base substrate, the gate dive circuit and the pixel drive circuits are located on the drive structure layer, the drive structure layer comprises: a semiconductor layer, a first conductive layer and a second conductive layer stacked sequentially on the base substrate; the semiconductor layer at least comprises: an active pattern of an output transistor and an active pattern of the noise reduction transistor is located on at least one drive output sub-circuit; a first conductive layer at least comprises: a second plate of an output capacitor located on at least one drive output sub-circuit; and a second conductive layer comprises: a first plate of an output capacitor, a gate electrode; a first electrode and a second of an output transistor, and a gate electrode, a first electrode and a second electrode of a noise reduction transistor located on at least one drive output sub-circuit, as claimed. Those skilled in the art would appreciate the ability to achieve higher resolution and better display quality in small-pixel displays.
Regarding claim 3:
Feng (in view of Takahashi and Zhu) discloses the display substrate according to claim 2, wherein a width-to-length ratio of a channel region of an active pattern of the output transistor in the N-th drive output sub-circuit is greater than a width-to-length ratio of a channel region of an active pattern of an output transistor in at least one of the first drive output sub-circuit to the (N-1)-th drive output sub-circuit (Takahashi Figure 7 width of register SRi is greater than SR1).
Regarding claim 5:
Feng (in view of Takahashi and Zhu) discloses the display apparatus according to claim 3, wherein a width-to-length ratio of a channel region of an active pattern of an output transistor in the first drive output sub-circuit is greater than a width-to-length ration of a channel region of an active pattern of an output transistor in at least one of a second drive output sub-circuit (Takahashi Figure 7 width of register SRi is greater than SR1).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al; (Publication number: US 2021/0166597 A1), hereafter Feng, in view of Baek et al; (Patent number: US 9, 311, 842 B2), hereafter Baek.
Regarding claim 28:
Feng discloses a display substrate (Feng Figure 12 and [0003] TFT-based LCD or AMOLED including gate drive on array (GOA))), comprising:
a first region and a second region (Feng Figure 12 first region corresponds to area of gate drive circuit 1210 and second region corresponds to display area of AMOELD or TFT-LCD display), wherein the first region is provided with pixel drive circuits arranged in an array (Feng [0003] inherent to AMOLED or TFT-based LCD), the second region is provided with a gate drive circuit configured to provide a drive signal to the pixel drive circuits (Feng Figure 12 and [0003] gate driving circuit configured as GOA type), the gate drive circuit comprises:
a plurality of shift registers (Feng Figure 10 see cascaded shift registers SR1, SR2, SR3, SR4; [0124])), at least one stage of shift register comprises:
a pre-circuit (Feng Figure 3 210-1) and a drive output circuit (Feng Figure 3 220-1), the pre-circuit is electrically connected to a signal input terminal (Feng Figure 3 terminal IN1 connected to circuit 210-1), a rest signal terminal and a cascaded output signal terminal respectively (Feng Figure 3 – sub-circuit 210-1 connected to terminal RST1 and output sub-circuit 220-1 via node PU), the drive output circuit is electrically connected to N drive signal output terminals respectively (Feng Figure 3 220-1 connected to cascaded output sub-circuits 220-N), a signal input terminal of at least one stage of at least one stage of shift register is electrically connected to a cascaded output signal terminal of at least one stage of shift register (Feng Figure 3 – terminal IN1 connected to terminal OUT1 of output sub-circuit 220-1 via node PU), a rest signal terminal of at least one stage of shift register is electrically connected to a cascaded output signal terminal of at least one stage of shift register (Feng Figure 3 – terminal RST1 of 250-1 connected to OUT1 of output sub-circuit 210-1 via nodes PU or VSS), the drive output circuit comprises: N drive output sub-circuits, an n-th drive output sub-circuit is electrically connected to an n-th output clock signal terminal (Feng Figure 6 each of 220-1 to 220-N connected to clock CLK1 – CLK-N); the second region is provided with M * N output clock signal lines, at least one output clock signal line at least partially extends in a second direction and is located on a side of the drive output circuit away from the first region, and a first output clock signal terminal to an N-th output clock signal terminal of at least one stage of shift register are electrically connected to N output clock signal lines respectively, M ≥ 2 (Feng Figure 7 – shift register includes additional clock signals CLKA at 270 in addition to CLK1 – CLKN).
Feng does not disclose for at least one stage of shift register, a line width of an output clock signal line connected to the N-th output clock signal terminal is larger than a line width of an output clock signal line connected to at least one of the first output clock signal terminal of an (N-1)-th output clock signal terminal.
However, Baek discloses a display device. More particularly, Baek discloses for at least one stage of shift register, a line width of an output clock signal line connected to the N-th output clock signal terminal is larger than a line width of an output clock signal line connected to at least one of the first output clock signal terminal of an (N-1)-th output clock signal terminal (Baek Figure 22; Col 16 lines 54 – 67).
It would have been obvious to modify Feng wherein at least one stage of shift register, a line width of an output clock signal line connected to the N-th output clock signal terminal is larger than a line width of an output clock signal line connected to at least one of the first output clock signal terminal of an (N-1)-th output clock signal terminal, as claimed. Those skilled in the art would appreciate providing a high degree of freedom for a design of a peripheral area in which a gate driver is disposed in a display device including the gate driver integrated on the display panel while further reducing an area of the peripheral area of the display panel (Baek Col1 lines 35 – 43).
Allowable Subject Matter
Claims 7, 11, 13, 14, 17, 18, 19, 20, 22, 24, 25, 28, 29, 32, and 36 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/MIHIR K RAYAN/ 3 September 2026Primary Examiner, Art Unit 2622
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