DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-16, 22, and 24 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 9, 12, 22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lindsay et al. (US 20030061300)
Regarding claim 1, Lindsay teaches
A device, comprising:
one or more interfaces (Fig. 1) configured to communicate with a plurality of random-access memories (RAM), wherein each RAM of the plurality of RAM is associated with an intellectual property (IP) initialization; (Fig. 1 (12a, 12b – dual port RAM), and [0032], “the sender performs initialization on the dual port RAM 12 whenever the sender comes out of "reset" in accordance with the preferred embodiment of the present invention.”)
processing circuitry configured to control the one or more interfaces and to: ([0012], “determining the validity of information communicated between two microprocessors using a dual port random access memory (RAM).”)
transmit a load message to each RAM of the plurality of RAM; and ([0033], “when the sender comes out of the reset state, the sender writes a value INIT_IN_PROGRESS to the INIT_STATUS memory location at step 102. The INIT_IN_PROGRESS state indicates that the sender is currently performing initialization on the dual port RAM, and the dual port RAM has not yet been initialized.” and [0035], “Each dual port RAM location (including the INIT_STATUS memory location) has a corresponding write flag, which is set when the dual port RAM location is updated.”)
determine, based on the load message, a status of each RAM of the plurality of RAM, the status indicating whether IP initialization associated with a respective RAM is finished or unfinished ([0034], “the sender continues to perform initialization on the dual port RAM at step 106. When the sender completes initialization, the sender then writes a value DPR_READY to the INIT_STATUS location at step 108. The DPR_READY state indicates that the sender has completed the initialization and also indicates that it is safe for the receiver to use the dual port RAM data.” And [0035], “Each dual port RAM location (including the INIT_STATUS memory location) has a corresponding write flag, which is set when the dual port RAM location is updated.”)
Regarding claim 2, Lindsay teaches wherein the processing circuitry is further configured to receive a response message from at least one RAM of the plurality of RAM comprising information about a status of the IP, initialization of the at least one RAM. ([0035], “ Each dual port RAM location (including the INIT_STATUS memory location) has a corresponding write flag, which is set when the dual port RAM location is updated … These write flags are cleared when the data signals are read by the receiver.”)
Regarding claim 5, Lindsay teaches wherein the load message is transmitted during a round of IP initialization, wherein the round of IP initialization has no order and at least two RAM of the plurality of RAM have an assigned IP initialization. ([0035], “After initialization of the dual port RAM is completed, the sender writes data signals to appropriate locations of the dual port RAM. In the preferred embodiment of the present invention, the communication protocol uses a write flag for handshake or semaphore purposes as described above. Each dual port RAM location (including the INIT_STATUS memory location) has a corresponding write flag, which is set when the dual port RAM location is updated. The write flags, which correspond to such locations containing data signals, get set at a logical one at the end of every dual port RAM update.” Where there is no predefined order in which each ram is loaded)
Regarding claim 9, Lindsay does not teach but Narasimhan teaches wherein the processing circuitry is further configured to communicate with the plurality of RAM by use of at least one of a mailbox or a register. ([0032], “an INIT_STATUS memory location is reserved in dual port RAM to keep track of initialization status.”)
Regarding claim 12, Van Alstyne teaches wherein the processing circuitry is further configured to: transmit a further load message to each RAM of the plurality of RAM from which a load message was received; and receive a further response message from each RAM of the plurality of RAM to which a further load message was transmitted. (Fig. 3)
As to claims 22 and 24, Lindsay teaches these claims according to the reasoning provided in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 10-11, and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lindsay in view of Van Alstyne et al. (US 20230273739)
Regarding claim 3, Lindsay does not teach but Van Alstyne teaches wherein the processing circuitry is further configured to transmit an adjustment message to at least one of the plurality of RAM, wherein the adjustment message is to adjust a setting of IP initialization of the at least one RAM of the plurality of RAM. (Fig. 2 (208-226), ([0052-53], “accelerated node 110 may create or configure a new RAM backed block device using the profile obtained in step 202. Once created, the block device will be added to unallocated block device pool 128. At step 217, MMA 142 may allocate the block device to a specific workload. This may effectively move the block device from unallocated block device pool 128 to allocated block device pool 124.”)
Van Alstyne and Lindsay are analogous art. Van Alstyne is cited to teach a similar concept of initialization of RAM. Van Alstyne teaches adjusting a RAM to adjust a setting of initialization. Based on Van Alstyne, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Lindsay to adjust an initialization setting. Furthermore, being able to configuring a mailbox for communication between a processor and RAM improves on Lindsay by being able to adjust an initialization memory to reallocate the memory and improve performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “In order to allow data from high performance local storage 120 to be backed up in the SDS system, MMA 142 may cause blocks or block devices of high performance local storage 120 to be added to the SDS system. … to allow such blocks or block devices of high performance local storage 120 to operate in its high-speed fashion so as to support to the operation of hardware accelerator 112”, (i.e. which improves performance).
Regarding claim 4, Lindsay does not teach but Van Alstyne teaches wherein the response message comprises a request for the adjustment message. (Fig. 2, ([0052-53], “accelerated node 110 may create or configure a new RAM backed block device using the profile obtained in step 202. Once created, the block device will be added to unallocated block device pool 128. At step 217, MMA 142 may allocate the block device to a specific workload. This may effectively move the block device from unallocated block device pool 128 to allocated block device pool 124.”)
Van Alstyne and Lindsay are analogous art. Van Alstyne is cited to teach a similar concept of initialization of RAM. Van Alstyne teaches using a message to reallocate memory. Based on Van Alstyne, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Lindsay to adjust an initialization setting. Furthermore, being able to use a message to reallocate memory improves on Lindsay by being able to adjust an initialization memory to reallocate the memory and improve performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “In order to allow data from high performance local storage 120 to be backed up in the SDS system, MMA 142 may cause blocks or block devices of high performance local storage 120 to be added to the SDS system. … to allow such blocks or block devices of high performance local storage 120 to operate in its high-speed fashion so as to support to the operation of hardware accelerator 112”, (i.e. which improves performance).
Regarding claim 10, Lindsay does not teach but Van Alstyne teaches wherein the processing circuitry is further configured to store the information about the IP initialization in a database. ([0036], “Node 110 may join an existing storage cluster, such as the SDS system provided by node 130, by any suitable method. As a result, node 110 may include a static configured data used to preprocess RAM backed block device that is local to node 110 or preconfigured in a boot image provided by, for example, a network boot mechanism. The system may instead use a dynamic configuration, including discovery or pull of object storage system bootstrap parameters from the existing static node(s). These parameters may include a set of block device profiles. These may be used to configure block devices when they are created.”)
Van Alstyne and Lindsay are analogous art. Van Alstyne is cited to teach a similar concept of initialization of RAM. Van Alstyne teaches adjusting initialization information in a table. Based on Van Alstyne, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Lindsay to initialization settings in a table. Furthermore, being able to adjust initialization information in a table and RAM improves on Lindsay by being able to organize an initialization memory to reallocate the memory and improve performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “In order to allow data from high performance local storage 120 to be backed up in the SDS system, MMA 142 may cause blocks or block devices of high performance local storage 120 to be added to the SDS system. … to allow such blocks or block devices of high performance local storage 120 to operate in its high-speed fashion so as to support to the operation of hardware accelerator 112”, (i.e. which improves performance).
Regarding claim 11, Lindsay does not teach but Van Alstyne teaches wherein a transmission of the adjustment message is based on the information about the IP initialization stored in the database. ([0036], “Node 110 may join an existing storage cluster, such as the SDS system provided by node 130, by any suitable method. As a result, node 110 may include a static configured data used to preprocess RAM backed block device that is local to node 110 or preconfigured in a boot image provided by, for example, a network boot mechanism. The system may instead use a dynamic configuration, including discovery or pull of object storage system bootstrap parameters from the existing static node(s). These parameters may include a set of block device profiles. These may be used to configure block devices when they are created.” And [0043], “This may include MMA 142 using an API to storage system manager 140 to control the reallocation of the RAM- storage block back to the overall storage pool controlled by system storage manager 134. When the high speed storage is no longer required by the assigned workload 113”.)
Van Alstyne and Lindsay are analogous art. Van Alstyne is cited to teach a similar concept of initialization of RAM. Van Alstyne teaches adjusting initialization information in a table. Based on Van Alstyne, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Lindsay to initialization settings in a table. Furthermore, being able to adjust initialization information in a table improves on Lindsay by being able to organize an initialization memory to reallocate the memory and improve performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “In order to allow data from high performance local storage 120 to be backed up in the SDS system, MMA 142 may cause blocks or block devices of high performance local storage 120 to be added to the SDS system. … to allow such blocks or block devices of high performance local storage 120 to operate in its high-speed fashion so as to support to the operation of hardware accelerator 112”, (i.e. which improves performance).
Regarding claim 13, Lindsay teaches wherein the processing circuitry is further configured to record a status of the plurality of IP initializations based on the further response messages. (Fig. 3, [0035], “Each dual port RAM location (including the INIT_STATUS memory location) has a corresponding write flag, which is set when the dual port RAM location is updated. … These write flags are cleared when the data signals are read by the receiver,” Where this process is repeated as shown in Fig. 3 (i.e. further response messages))
Regarding claim 14, Lindsay does not teach but Van Alstyne teaches wherein the processing circuitry is further configured to mark a resource information in a resource database based on the adjustment message. ([0039], “MMA 142 may create a storage class to tag the newly added storage as self-determinative as to replication to signify the ability for MMA 142 to control replication. The tag and replication attribute may be contained in the block storage device profiles retrieved during the boot process.”)
Van Alstyne and Lindsay are analogous art. Van Alstyne is cited to teach a similar concept of initialization of RAM. Van Alstyne teaches marking a resource in a database. Based on Van Alstyne, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Lindsay to mark a resource in a database. Furthermore, being able to mark a resource in a database between a processor and RAM improves on Lindsay by being able to organize an initialization memory to reallocate the memory and improve performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “In order to allow data from high performance local storage 120 to be backed up in the SDS system, MMA 142 may cause blocks or block devices of high performance local storage 120 to be added to the SDS system. … to allow such blocks or block devices of high performance local storage 120 to operate in its high-speed fashion so as to support to the operation of hardware accelerator 112”, (i.e. which improves performance).
Regarding claim 15, Van Alstyne teaches wherein the processing circuitry is further configured to mark a resource information in a resource database based on the further response message and the adjustment message. (Fig. 2, [0039], “MMA 142 may create a storage class to tag the newly added storage as self-determinative as to replication to signify the ability for MMA 142 to control replication. The tag and replication attribute may be contained in the block storage device profiles retrieved during the boot process.” Where the process loops and is repeated based on new block device requests in fig. 2)
Van Alstyne and Lindsay are analogous art. Van Alstyne is cited to teach a similar concept of initialization of RAM. Van Alstyne teaches marking a resource in a database. Based on Van Alstyne, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Lindsay to mark a resource in a database. Furthermore, being able to mark a resource in a database between a processor and RAM improves on Lindsay by being able to organize an initialization memory to reallocate the memory and improve performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “In order to allow data from high performance local storage 120 to be backed up in the SDS system, MMA 142 may cause blocks or block devices of high performance local storage 120 to be added to the SDS system. … to allow such blocks or block devices of high performance local storage 120 to operate in its high-speed fashion so as to support to the operation of hardware accelerator 112”, (i.e. which improves performance).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lindsay in view of Applicant Admitted Prior Art (AAPA).
Regarding claim 16, Lindsay teaches a plurality of RAM and cores but does not specifically teach a RAM assigned to a micro core teaches wherein each RAM of the plurality of RAM is assigned to a microcore.
AAPA teaches a RAM assigned to a micro core teaches wherein each RAM of the plurality of RAM is assigned to a microcore. (Fig. 4 (Prior Art shows IP A, IP B, and IP C allocated via individual SRAMs to micro cores 0, 1, 2, and 3)
Lindsay and AAPA are analogous art. AAPA is cited to teach a similar concept of initialization of RAM. AAPA teaches allocating each RAM is assigned to a micro core as a known technique. Based on AAPA and the KSR rational of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Van Alstyne to allocating each RAM is assigned to a micro core.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p.
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 September 19, 2026
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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