Prosecution Insights
Last updated: October 23, 2026
Application No. 18/845,921

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Non-Final OA §102§103
Filed
Sep 11, 2024
Priority
Mar 14, 2022 — RE 10-2022-0031539 +3 more
Examiner
SEDOROOK, DAVID PAUL
Art Unit
Tech Center
Assignee
Jusung Engineering Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
146 granted / 159 resolved
+31.8% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
26 currently pending
Career history
191
Total Applications
across all art units

Statute-Specific Performance

§103
64.1%
+24.1% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 159 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendments filed on 9/11/2024 have been entered. Claims 1-19 remain pending. Claims 20-34 were cancelled. Claim Objections Claim 6 is objected to because of the following informalities: it appears the claim language “wherein each of the oxide of the first metal element and the oxide of the second metal element contains zinc oxide doped with a plurality impurities” should read as “wherein each of the oxide of the first metal element and the oxide of the second metal element contains zinc oxide doped with a plurality of impurities.” Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 4-5, 11-15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al (KR 20200083211 A). Regarding Claim 1, Yamazaki et al discloses a thin film transistor (transistor 200 [page 17, lines 13-23] Fig 4B) comprising: a gate electrode (conductor 260/260a, 260b [page 19, lines 29-44] Fig 4B); an active layer (230/230a, 230b, 230c [page 17, lines 13-45] Fig 4) containing an oxide of a first metal element (may be a metal oxide with gallium as M, In-M-Zn oxide [page 13, lines 20-40] Fig 4) and disposed to be vertically spaced apart from the gate electrode (260/260a, 260b Fig 4); a source electrode (conductor 242a, 242b (left) [page 12, lines 38-44] and conductor 240a, 240b (left) [page 12, lines 1-37] Fig 4) and a drain electrode (conductor 242a, 242b (right) [page 12, lines 38-44] and 240a,b (right) [page 12, lines 1-37] Fig 4) disposed to be spaced apart from each other on the active layer (230/230a, 230b, 230c Fig 4); and a contact layer (oxide 243/243a, 243b [page 12, lines 38-44] Fig 4) containing a second metal element (may be a metal oxide with aluminum, In-M-Zn oxide [page 17, lines 13-33] Fig 4) and disposed between the active layer (230/230a, 230b, 230c Fig 4) and the source (240a, 240b, 242a, 242b (left) Fig 4) and drain electrodes (240a, 240b, 242a, 242b (right) Fig 4). Regarding Claim 2, Yamazaki et al discloses the limitations of claim 1 as explained above. Yamazaki et al further discloses wherein the contact layer (oxide 243/243a, 243b [page 12, lines 38-44] Fig 4) contains a metal or an alloy containing the second metal element (243/243a, 243b Fig 4 contains aluminum). Regarding Claim 4, Yamazaki et al discloses the limitations of claim 1 as explained above. Yamazaki et al further discloses wherein the contact layer (243/243a, 243b Fig 4) contains an oxide of the second metal element (aluminum oxide). Regarding Claim 5, Yamazaki et al discloses the limitation of claim 4 as explained above. Yamazaki et al further discloses wherein the oxide of the first metal element (230 may be a metal oxide with gallium as M, In-M-Zn oxide [page 13, lines 20-40] Fig 4) and the oxide of the second metal element (243 may be a metal oxide with aluminum, In-M-Zn oxide [page 17, lines 13-33] Fig 4) have compositions different from each other. Regarding Claim 11, Yamazaki et al discloses the limitation of claim 1 as explained above. Yamazaki et al further discloses wherein the contact layer (243/243a, 243b Fig 4) has a thickness of approximately 30 Å to approximately 100 Å (243 may have a thickness of 3 nm (30 angstroms) [page 17, lines 13-33]). Regarding Claim 12, Yamazaki et al discloses the limitation of claim 1 as explained above. Yamazaki et al further discloses further comprising an insulating layer (insulator 280 [page 8, lines 10-15] Fig 4 and Fig 22B) disposed on the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B) and having a contact hole (shown in annotated Fig 11B) through which a portion of a surface of the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B) is exposed, wherein the contact layer (243/243a, 243b Fig 4 and Fig 22B) is disposed on the portion of the surface of the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B), which is exposed by the contact hole (shown in annotated Fig 11B), and the source and drain electrodes (source and drain electrodes/conductor 242/242a, 242b [page 12, lines 39-44]-[page 13, line 1] Fig 4 and Fig 22B) are in contact with the contact layer (243/243a, 243b Fig 4 and Fig 22B) to extend onto the insulating layer (280 Fig 4 and Fig 22B). PNG media_image1.png 640 659 media_image1.png Greyscale Regarding Claim 13, Yamazaki et al discloses a method for manufacturing (method for manufacturing [page 27, lines 18-27] Fig 4) a thin film transistor (transistor 200 [page 17, lines 13-23] Fig 4B), the method comprising: preparing a substrate (preparing a substrate (not shown) [page 27, lines 23-26]) on which a gate electrode (conductor 260/260a, 260b [page 19, lines 29-44] Fig 4B) and an active layer (230/230a, 230b, 230c [page 17, lines 13-45] Fig 4) disposed to be vertically spaced apart from the gate electrode (260/260a, 260b Fig 4) are formed; and forming a contact layer (oxide 243/243a, 243b [page 12, lines 38-44] Fig 4) for connecting the active layer (230/230a, 230b, 230c Fig 4) to source (conductor 242a, 242b (left) [page 12, lines 38-44] and conductor 240a, 240b (left) [page 12, lines 1-37] Fig 4) and drain electrodes (conductor 242a, 242b (right) [page 12, lines 38-44] and conductor 240a, 240b (right) [page 12, lines 1-37] Fig 4) on the active layer (230/230a, 230b, 230c Fig 4). Regarding Claim 14, Yamazaki et al discloses the limitations of claim 13 as explained above. Yamazaki et al further discloses wherein the preparing of the substrate comprises preparing the substrate (preparing a substrate (not shown) [page 27, lines 23-26]) on which an insulating layer (insulator 280 [page 8, lines 10-15] Fig 4 and Fig 22B) having a contact hole (shown in annotated Fig 11B), through which a portion of a surface of the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B) is exposed, on the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B), and the forming of the contact layer (243/243a, 243b Fig 4 and Fig 22B) comprises forming the contact layer on the portion of the surface of the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B), which is exposed by the contact hole (shown in annotated Fig 11B). PNG media_image1.png 640 659 media_image1.png Greyscale Regarding Claim 15, Yamazaki et al discloses the limitations of claim 14 as explained above. Yamazaki et al further discloses wherein, in the forming of the contact layer (243/243a, 243b Fig 4 and Fig 22B), the contact layer (243/243a, 243b Fig 4 and Fig 22B) is formed to a thickness of approximately 30 Å to approximately 100 Å (243 may have a thickness of 3 nm (30 angstroms) [page 17, lines 13-33]) on the portion of the surface of the active layer (230/230a, 230b, 230c Fig 4 and Fig 22B). Regarding Claim 19, Yamazaki et al discloses the limitation of claim 13 as explained above. Yamazaki et al further discloses further comprising forming a source electrode (conductor 242a, 242b (left) [page 12, lines 38-44] and conductor 240a, 240b (left) [page 12, lines 1-37] Fig 4) and a drain electrode (conductor 242a, 242b (right) [page 12, lines 38-44] and conductor 240a, 240b (right) [page 12, lines 1-37] Fig 4) on the contact layer (oxide 243/243a, 243b [page 12, lines 38-44] Fig 4). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over by Yamazaki et al (KR 20200083211 A) in view of Chu et al (US 2023/0253308). Regarding Claim 3, Yamazaki et al discloses the limitations of claim 1 as explained above. Yamazaki et al does not disclose wherein the second metal element comprises ruthenium. Chu et al, in the related art of semiconductor devices that include transistors, discloses a contact layer (first contact layer 5a is made of ruthenium [0022] Fig 5) that comprises ruthenium. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki et al to include a contact layer that comprises ruthenium as taught by Chu et al in order to optimize electrical performance while meeting small size parameters. Further, a person of ordinary skill in the art would have recognized that having a contact layer comprising ruthenium would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate). Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over by Yamazaki et al (KR 20200083211 A) in view of Luo (US 2020/0411567). Regarding Claim 6, Yamazaki et al discloses the limitations of claim 1 as explained above. Yamazaki et al does not directly disclose wherein each of the oxide of the first metal element and the oxide of the second metal element contains zinc oxide doped with a plurality of impurities, and the oxide of the first metal element and the oxide of the second metal element have contents of the impurities, which are different from each other. Luo, in the related art of semiconductor devices that include IGZO devices, discloses wherein each of the oxide (IGZO [0051]) of the first metal element (first active layer 401 [0051] Fig 7) and the oxide (IGZO [0051]) of the second metal element (second active layer 402 [0051] Fig 7) contains zinc oxide (IGZO [0051]) doped with a plurality of impurities (ion doping concentration [0051]), and the oxide (IGZO [0051]) of the first metal element (401 Fig 7) and the oxide (IGZO [0051]) of the second metal element (402 Fig 7) have contents of the impurities (ion doping concentration, doped ions may be oxygen but is not limited thereto [0051]), which are different (different [0051]) from each other. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki et al to include wherein each of the oxide of the first metal element and the oxide of the second metal element contains zinc oxide doped with a plurality of impurities, and the oxide of the first metal element and the oxide of the second metal element have contents of the impurities, which are different from each other as taught by Luo in order to reduce the depletion area of the active layer, optimize the on-state current of the thin film transistor [0028]. Further, a person of ordinary skill in the art would have recognized that having doping concentrations different from one another would optimize the electron mobility and diffusion within the layers of the device (see MPEP 2143.I(D)). Regarding Claim 10, the combination of Yamazaki et al and Luo discloses the limitations of claim 6 as explained above. The combination of Yamazaki et al and Luo further discloses wherein the oxide (IGZO [0051] Luo) of the second metal element (402 Fig 7 Luo) has a content of oxygen (O) ([0051] Luo) less than that of the oxide (IGZO [0051] Luo) of the first metal element (401 Fig 7 Luo). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over by Yamazaki et al (KR 20200083211 A) in view of Luo (US 2020/0411567), and in further view of Quan et al (CN 106169480 B). Regarding Claim 9, the combination of Yamazaki et al and Luo discloses the limitations of claim 6 as explained above. The combination of Yamazaki et al and Luo does not directly disclose wherein the oxide of the first metal element contains the impurities of approximately 20 at% or more and less than approximately 40 at% with respect to the entire oxide of the first metal element, and the oxide of the second metal element contains impurities of approximately 40 at% or more and less than approximately 60 at% with respect to the entire oxide of the second metal element. Quan et al, in the related art of semiconductor devices that include metal oxide semiconductor devices, discloses wherein the content of the oxide semiconductor material of the doped material is 1 to 5 atomic percent of the oxide semiconductor material [page 4, lines 16-18]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yamazaki et al and Luo to include wherein the oxide of the first metal element contains the impurities of approximately 20 at% or more and less than approximately 40 at% with respect to the entire oxide of the first metal element, and the oxide of the second metal element contains impurities of approximately 40 at% or more and less than approximately 60 at% with respect to the entire oxide of the second metal element as taught by Quan et al in order to overcome defects and ensure a constant current of high reliability under stress conditions [page 4, lines 2-6] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by Yamazaki et al (KR 20200083211 A) in view of Luo (US 2020/0411567), and in further view of Kim et al (US 2023/0071089). Regarding Claim 7, the combination of Yamazaki et al and Luo discloses the limitations of claim 6 as explained above. The combination of Yamazaki et al and Luo does not directly disclose wherein the oxide of the second metal element has a content of the impurities, which is greater than that of the oxide of the first metal element. Kim et al, in the related art of semiconductor devices that include IGZO devices, discloses wherein the content of the impurities are molybdenum Mo [0060]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yamazaki et al and Luo to include wherein the content of the impurities are molybdenum Mo as taught by Kim et al in order to reduce carriers and a current change rate relative to a voltage thereby improving function of the thin film transistor [0059]. Further, a person of ordinary skill in the art would have recognized that having Mo as the impurity would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate). The combination of Yamazaki et al, Luo, and Kim et al now discloses wherein the oxide (IGZO [0051] Luo) of the second metal element (402 Fig 7 Luo) has a content of the impurities (Mo Kim et al), which is greater (the examiner notes that since the oxide impurity of the first metal element (401 Luo) is greater than the oxide impurity of the second metal element (402 Luo), that the impurity (Mo Kim et al) of the first metal element (402 Luo) would be greater than that of the first metal element )401 Luo)) than that of the oxide (IGZO [0051] Luo) of the first metal element (401 Fig 6 Luo). Regarding Claim 8, the combination of Yamazaki et al and Luo discloses the limitations of claim 6 as explained above. The combination of Yamazaki et al and Luo does not directly disclose wherein the impurities comprise at least one of indium (In), gallium (Ga), tungsten (W), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), manganese (Mn), technetium (Tc), rhenium (Re), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), boron (B), thallium (Tl), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), phosphorus (P), or arsenic (As). Kim et al, in the related art of semiconductor devices that include IGZO devices, discloses wherein the content of the impurities are molybdenum Mo [0060]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yamazaki et al and Luo to include wherein the content of the impurities are molybdenum Mo as taught by Kim et al in order to reduce carriers and a current change rate relative to a voltage thereby improving function of the thin film transistor [0059]. Further, a person of ordinary skill in the art would have recognized that having Mo as the impurity would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate). Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over by Yamazaki et al (KR 20200083211 A). Regarding Claim 16, Yamazaki et al discloses the limitations of claim 13 as explained above. Yamazaki et al further discloses wherein the forming of the contact layer (oxide 243/243a, 243b [page 12, lines 38-44] Fig 4) is performed by an atomic layer deposition (ALD [page 31, lines 32-44]) process in which a process cycle comprising supplying a source gas containing a metal element (In:Ga:Zn [page 31, lines 32-44]) onto the active layer (230/230a, 230b, 230c [page 17, lines 13-45] Fig 4) and supplying a reactant gas containing oxygen (oxide [page 31, lines 32-44]) onto the active layer (230/230a, 230b, 230c Fig 4). Yamazaki et al, as applied to claim 13, does not directly disclose the atomic layer deposition method that is repeated. However, in a different embodiment, Yamazaki et al, in the related art of semiconductor devices that include transistors, discloses an atomic layer deposition method (ALD [page 31, lines 32-44]) that is repeated [page 21, lines 22-26]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki et al, as applied to claim 13, to include wherein an atomic layer deposition method is repeated in order to for a film with a high aspect ratio, few defects, and excellent coatability [page 21, lines 27-31]. Further, a person of ordinary skill in the art would have recognized that having a film with few defects would be advantageous in improving the quality, durability, and reliability of the device (see MPEP 2143.I(D). Additionally, a person of ordinary skill in the art would have recognized that using a repetitive ALD method would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate). Regarding Claim 17, Yamazaki et al discloses the limitations of claim 16 as explained above. Yamazaki et al further discloses wherein, in the supplying of the source gas, a first source gas containing zinc (Zn) (In:Ga:Zn [page 31, lines 32-44]) and a second source gas containing at least one of indium (In) (In:Ga:Zn [page 31, lines 32-44]), gallium (Ga) (In:Ga:Zn [page 31, lines 32-44]), tungsten (W), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), manganese (Mn), technetium (Tc), rhenium (Re), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), boron (B), thallium (Tl), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), phosphorus (P), or arsenic (As) are supplied at the same time. Regarding Claim 18, Yamazaki et al discloses the limitations of claim 17 as explained above. Yamazaki et al further discloses wherein, in the supplying of the source gas, the source gas is controlled to be supplied so that a supply amount of the second source gas (In: Ga: 2: 2 [page 31, lines 20-31]) is greater than a supply amount of the first source gas (Zn: 1 [page 31, lines 20-31]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yamazaki et al, as applied to claim 17, to include wherein the supply amount of indium and gallium is greater than the supply amount of zinc as taught by Yamazaki et al in order to optimize the reliability of the device [page 31, lines 19-31]. Further, a person of ordinary skill in the art would have recognized that the ratio of In:Ga:Zn = 2:2:1 would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B))(suitable alternate). Related Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsutsumi et al (US 2017/0247802) which discloses an atomic layer deposition method that is repeated [0123], and Min (US 2017/0133475) which discloses an atomic layer deposition process [0008]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.P.S./Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Sep 11, 2024
Application Filed
Oct 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+7.1%)
3y 0m (~11m remaining)
Median Time to Grant
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