DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore,
the limitation of claim 13 that recites traces having smaller width than subsequent/secondary conductive pillars
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Huo et al. (CN-213782012, hereafter Huo).
Regarding claim 1, Huo discloses a fabrication method for a semiconductor structure, comprising: providing a to-be-wired structure (10), wherein the to-be-wired structure comprises at least one chip (20), the chip comprises a front surface, and the front surface of the chip is provided with pads (21) (Fig. 3); forming a first insulating layer (22) on the front surface of the chip, wherein the first insulating layer is provided with openings (23), and each of the openings exposes at least part of one of the pads; forming a conductive film layer (41/24) on a side of the first insulating layer facing away from the chip, wherein the conductive film layer covers a surface of the first insulating layer facing away from the chip and portions of the pads exposed by the openings (Fig. 6), removing a portion of the conductive film layer exceeding the first insulating layer to obtain conductive structures located in the openings and in direct contact with the pads (pg. 10, par. 3); and forming a redistribution structure (41) on the side of the first insulating layer facing away from the chip, wherein the redistribution structure is electrically connected to the conductive structures (24) (Fig. 6-7).
Huo fails to explicitly disclose a thickness of a portion of the conductive film layer located on the side of the first insulating layer facing away from the chip is less than a thickness of a portion of the conductive film layer covering the pads.
However, in another embodiment, Huo teaches a thickness of a portion of the conductive film layer (61) located on the side of the first insulating layer facing away from the chip is less than a thickness of a portion of the conductive film layer covering the pads (Fig. 14).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo by providing a film layer with greater thickness on the pad than on the top of the insulating layer because directional ion biasing or surface treatments accelerate metal deposition onto the pad while suppressing resputtering growth on the surface.
Regarding claim 2, Huo discloses a fabrication method for the semiconductor structure wherein the to-be-wired structure comprises more than one chips (pg. 4, par. 8); and providing the to-be-wired structure comprises: providing a wafer (10, Fig. 3), wherein the wafer comprises chips connected together (pg. 4, par. 11).
Regarding claim 6, Huo discloses a fabrication method for the semiconductor structure wherein forming the conductive film layer on the side of the first insulating layer facing away from the chip, wherein the conductive film layer covers the surface of the first insulating layer facing away from the chip, side surfaces of the openings, and the portions of the pads exposed by the openings comprises: disposing a first seed layer (pg. 6, par. 8-10) on the surface of the first insulating layer (22) facing away from the chip (20), the side surfaces of the openings (23), and the portions of the pads (21) exposed by the openings; and forming the conductive film layer based on the first seed layer (Fig. 5-6).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Chen et al. (CN-111599694, hereafter Chen).
Regarding claim 3, Huo discloses a fabrication method for the semiconductor structure wherein after forming the first insulating layer on the front surface of the chip, the fabrication method for the semiconductor structure further comprises: cutting the wafer (pg. 4, par. 14) to obtain semiconductor intermediate structures, wherein each of the semiconductor intermediate structures comprises at least one of the chips (pg. 4, par. 11); mounting the semiconductor intermediate structure on a first carrier (10), wherein the first insulating layer (22) faces the first carrier; forming a molding layer (30), wherein the molding layer covers at least side surfaces of the semiconductor intermediate structure (Fig. 3-4); stripping the first carrier to obtain a molding structure (Fig. 5).
Huo fails to disclose mounting the molding structure on a second carrier, wherein the first insulating layer faces away from the second carrier.
However, Chen teaches mounting the molding structure on a second carrier (103), wherein the first insulating layer faces away from the second carrier (Fig. 9).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Chen by mounting the molding structure on a second carrier in order to support fragile structures during processing and facilitate subsequent processing.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Di et al. (CN-106098664, hereafter Di) and Chew (2018/0204741, hereafter Chew).
Regarding claim 4, Huo, discussed above, fails to disclose a fabrication method for the semiconductor structure wherein providing the to-be-wired structure comprises: providing a silicon substrate and a chip, wherein the silicon substrate is provided with a groove, and a front surface of the chip faces away from a bottom of the groove; and placing the chip in the groove; and filling a glue material between the chip and a sidewall of the groove, and curing the glue material to form a dielectric layer.
However, Di teaches a fabrication method for the semiconductor structure wherein providing the to-be-wired structure comprises: providing a silicon substrate (200) and a chip (100), wherein the silicon substrate is provided with a groove (210), and a front surface of the chip faces away from a bottom of the groove; and placing the chip in the groove; and filling a glue material (301) between the chip and a sidewall of the groove (Fig. 8-9).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Di by placing a chip in a substrate groove in order to minimize package thickness, provide alignment, and shorten electrical paths.
Further, Chew teaches curing the glue material to form a dielectric layer (par. 0131).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo and Di with Chew by providing and curing glue in order to secure the die, electrically insulate it, and fill voids to enhance thermal expansion matching and stress redistribution.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Chew.
Regarding claim 5, Huo discloses patterning a portion of the encapsulation layer (22) located on the front surface of the chip to form the openings (23) exposing the pads (Fig. 5).
Huo fails to disclose a fabrication method for the semiconductor structure wherein providing the to-be-wired structure comprises: providing a third carrier and chips, and mounting the chips on the third carrier, wherein front surfaces of the chips face away from the third carrier; and forming the first insulating layer on the front surface of the chip comprises: forming an encapsulation layer covering side surfaces of the chip and the front surface of the chip;… wherein the first insulating layer comprises a portion of the encapsulation layer located on the front surface of the chip.
However, Chew teaches a fabrication method for the semiconductor structure wherein providing the to-be-wired structure comprises: providing a third carrier (200) and chips (201), and mounting the chips on the third carrier, wherein front surfaces of the chips face away from the third carrier (Fig. 2c); and forming the first insulating layer on the front surface of the chip comprises: forming an encapsulation layer (204) covering side surfaces of the chip and the front surface of the chip; wherein the first insulating layer (203) comprises a portion of the encapsulation layer located on the front surface of the chip (Fig. 2c).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Chew by forming an encapsulation layer comprised by the insulating layer in order to protect the die from mechanical damage, moisture, and thermal stress while electrically isolating and routing subsequent layers.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Di.
Regarding claim 7, Huo discloses a fabrication method for the semiconductor structure wherein: removing the portion of the conductive film layer exceeding the first insulating layer comprises: etching the conductive film layer to remove the portion of the conductive film layer exceeding the first insulating layer (pg. 6, par. 12); or removing the portion of the conductive film layer exceeding the first insulating layer comprises: thinning the conductive film layer to remove the portion of the conductive film layer exceeding the first insulating layer (pg. 6, par. 12).
Huo fails to disclose after removing the portion of the conductive film layer exceeding the first insulating layer, the fabrication method for the semiconductor structure further comprises: thinning a portion of the conductive film layer in the openings and the first insulating layer, so that the surface of the first insulating layer facing away from the chip aligns with surfaces of the obtained conductive structures facing away from the chip.
However, Di teaches after removing the portion of the conductive film layer exceeding the first insulating layer, the fabrication method for the semiconductor structure further comprises: thinning a portion of the conductive film layer in the openings and the first insulating layer, so that the surface of the first insulating layer facing away from the chip aligns with surfaces of the obtained conductive structures facing away from the chip (pg. 4, par. 8).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Di by thinning the film to align the surface of the insulating layer with the conductive structures in order to eliminate surface topography and enable multi-layer redistribution or bonding.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Suk et al. (2020/0083201, hereafter Suk).
Regarding claim 8, Huo discloses a fabrication method for the semiconductor structure wherein the redistribution structure (40) comprises a redistribution layer on a side of the conductive structures facing away from the chip (20) (Fig. 6).
Huo fails to disclose forming the redistribution structure on the side of the first insulating layer facing away from the chip comprises: forming a second seed layer on the side of the conductive structures facing away from the chip; and forming the redistribution layer based on the second seed layer.
However, Suk teaches forming the redistribution structure on the side of the first insulating layer facing away from the chip comprises: forming a second seed layer (122) on the side of the conductive structures facing away from the chip; and forming the redistribution (132) layer based on the second seed layer (Fig. 1H).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Suk by forming a second seed layer and redistribution structure in order to build multi-layer routing networks, allowing vertical and horizontal communication across the package.
Regarding claim 9, Huo discloses forming the redistribution layer based on the second seed layer comprises: disposing a patterned insulating material layer on a side of the second seed layer facing away from the chip, wherein the insulating material layer is provided with hollow portions, and an orthographic projection of each of the hollow portions on the second seed layer overlaps with an orthographic projection of one of the conductive structures on the second seed layer; connecting the second seed layer to a power for electroplating to form trace structures in the hollow portions; and removing the insulating material layer and a portion of the second seed layer not covered by the trace structures to obtain the redistribution layer, wherein the redistribution layer comprises the trace structures and the remaining second seed layer (pg. 6, par. 7-12).
Huo fails to disclose a fabrication method for the semiconductor structure wherein the second seed layer covers surfaces of the conductive structures facing away from the chip and a surface of the first insulating layer facing away from the chip.
However, Suk teaches a fabrication method for the semiconductor structure wherein the second seed layer (122) covers surfaces of the conductive structures (131) facing away from the chip and a surface of the first insulating layer (113) facing away from the chip (Fig. 1H).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Suk by providing a seed layer over the conductive structures in order to establish continuous, low-resistance contact and adhesion interface enabling reliable electroplating and signal routing to subsequent layers.
Regarding claim 10, Huo discloses a fabrication method for the semiconductor structure wherein after removing the insulating material layer and the portion of the second seed layer not covered by the redistribution trace structures, forming the redistribution structure on the side of the first insulating layer facing away from the chip further comprises: forming conductive pillars (52) on a side of the redistribution layer (40) facing away from the chip (40) to obtain the redistribution structure comprising the redistribution layer and the conductive pillars (Fig. 8-10); wherein the fabrication method for the semiconductor structure further comprises: forming a second insulating layer (50); wherein the second insulating layer covers the redistribution layer and the conductive pillars, and surfaces of the conductive pillars facing away from the chip are exposed from the second insulating layer; forming the second insulating layer is performed before forming the conductive pillars on the side of the redistribution layer facing away from the chip; the second insulating layer is provided with through holes (51) exposing the redistribution layer, and forming the conductive pillars on the side of the redistribution layer facing away from the chip comprises: forming the conductive pillars on the side of the redistribution layer facing away from the chip in the through holes (Fig. 8-10).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Liu (CN-110783327, hereafter Liu).
Regarding claim 11, Huo discloses semiconductor structure, comprising: a to-be-wired structure (10), wherein the to-be-wired structure comprises at least one chip (20), the chip comprises a front surface, and the front surface of the chip is provided with pads (21); a first insulating layer (22) on the front surface of the chip, wherein the first insulating layer is provided with openings (23), and each of the openings exposes at least part of one of the pads; conductive structures (24) located in the openings and in direct contact with the pads; and a redistribution structure (41) located on a side of the first insulating layer facing away from the chip (Fig. 3-6).
Huo fails to disclose wherein the redistribution structure comprises wirings, and the wirings are in direct contact with the conductive structures; for each of the wirings, a width of a portion of the wiring in contact with the corresponding conductive structure is less than a width of a surface of the corresponding conductive structure facing away from the chip.
However, Liu teaches wherein the redistribution structure comprises wirings (150), and the wirings are in direct contact with the conductive structures (110); for each of the wirings, a width of a portion of the wiring in contact with the corresponding conductive structure is less than a width of a surface of the corresponding conductive structure facing away from the chip (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Liu by providing wirings that have less width than the conductive structures in order to bridge lateral layout offsets, fan out signal lines, and redistribute contacts, while reducing thermal stress and minimizing parasitic capacitance.
Regarding claim 12, Huo discloses a semiconductor structure wherein the redistribution structure (40) further comprises conductive pillars (52) on a side of the wirings (from Liu) facing away from the chip (20) and a second insulating layer (50), the second insulating layer covers the wirings and the conductive pillars, and surfaces of the conductive pillars facing away from the chip are exposed from the second insulating layer (Fig. 10).
Regarding claim 13, Huo discloses semiconductor structure further comprising a first redistribution layer (60) on a side of the redistribution structure (40) facing away from the chip; the first redistribution layer comprises conductive traces (61), the conductive traces are in direct contact with the conductive pillars (52), and for each of the conductive traces (Fig. 10).
Huo fails to disclose a width of a portion of the conductive trace in contact with the corresponding conductive pillar is less than a width of a surface of the corresponding conductive pillar facing away from the chip.
However, Liu teaches a width of a portion of the conductive trace (150 lower) in contact with the corresponding conductive pillar (150 upper) is less than a width of a surface of the corresponding conductive pillar facing away from the chip (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo with Liu by providing a trace with less width than the conductive pillar in order to reduce thermal stress and minimize parasitic capacitance.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Liu as applied to claim 11 above, and further in view of Di.
Regarding claim 14, Huo and Liu, discussed above, fail to disclose a semiconductor structure wherein the to-be-wired structure further comprises a silicon substrate and a dielectric layer; the silicon substrate is provided with a groove, the chip is located in the groove, and the front surface of the chip faces away from a bottom of the groove; and the dielectric layer is filled between the chip and a sidewall of the groove.
However, Di teaches a semiconductor structure wherein the to-be-wired structure further comprises a silicon substrate (200) and a dielectric layer (301); the silicon substrate is provided with a groove (201), the chip (100) is located in the groove, and the front surface of the chip faces away from a bottom of the groove; and the dielectric layer is filled between the chip and a sidewall of the groove (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo and Liu with Di by placing a chip in a substrate groove in order to minimize package thickness, provide alignment, and shorten electrical paths.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Huo in view of Liu as applied to claim 1 above, and further in view of Suk.
Regarding claim 15, Huo and Liu, discussed above, fail to disclose a semiconductor structure wherein, the to-be-wired structure further comprises a molding layer, and the molding layer covers at least side surfaces of the chip; the molding layer is provided with a first through hole penetrating through the molding layer, and the semiconductor structure further comprises a first conductive portion located in the first through hole and a second redistribution layer located on a side of the molding layer facing away from the redistribution structure; and the second redistribution layer is electrically connected to the redistribution structure through the first conductive portion; or the to-be-wired structure further comprises a silicon substrate and a dielectric layer; the silicon substrate is provided with a groove and a second through hole penetrating through the silicon substrate, the chip is located in the groove, and the dielectric layer is filled between the chip and a side wall of the groove; the semiconductor structure further comprises a second conductive portion located in the second through hole and a third redistribution layer located on a side of the silicon substrate facing away from the redistribution structure; and the third redistribution layer is electrically connected with the redistribution structure through the second conductive portion.
However, Suk teaches a semiconductor structure wherein, the to-be-wired structure further comprises a molding layer (300), and the molding layer covers at least side surfaces of the chip (200); the molding layer is provided with a first through hole penetrating through the molding layer, and the semiconductor structure further comprises a first conductive portion (520) located in the first through hole and a second redistribution layer (600) located on a side of the molding layer facing away from the redistribution structure (100); and the second redistribution layer is electrically connected to the redistribution structure through the first conductive portion (Fig. 7C); or the to-be-wired structure further comprises a silicon substrate and a dielectric layer; the silicon substrate is provided with a groove and a second through hole penetrating through the silicon substrate, the chip is located in the groove, and the dielectric layer is filled between the chip and a side wall of the groove; the semiconductor structure further comprises a second conductive portion located in the second through hole and a third redistribution layer located on a side of the silicon substrate facing away from the redistribution structure; and the third redistribution layer is electrically connected with the redistribution structure through the second conductive portion (see former).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Huo and Liu with Suk by providing a molding and a conductive portion connecting redistribution layers on both sides of the chip in order to enable two-sided integration, allowing the package to interface with mounted components and connections while shortening signal paths.
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/C.M.B./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
