DETAILED ACTION
This communication is in response to the Amendment filed on February 20, 2026 in which claims 1-15 and 21-25 are pending in the application. Claims 1, 12, and 21 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Final Office Action is in response to the applicant’s remarks and arguments filed on February 20, 2026.
Claims 16-20 are canceled. Claims 1 and 12 are amended.
Claims 21-25 are added.
Claims 1-15 and 21-25 remain pending in the application and are being considered on the merits.
Response to Arguments
The applicant’s remarks and/or arguments, filed on February 20, 2026 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Applicant's arguments in the applicant’s remarks and amendments with regard to independent claims 1-6, 9-13 and 15-20, found on pages 1-5 and filed on February 20, 2026, have been fully considered and are persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C 103 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art: (US 2020/0333975 A1) issued to Benisty, and JP 5811245 B1 issued to NEC Corp ‘245 in view of the previously cited prior art(s).
Applicant argues “Claim 1 is thus presently amended to clarify (1) the fence counter is incremented responsive to the first fence instruction including a first fence participant bit indicating fence participation, i.e., the increment operation is conditional upon the presence and state of a fence participant bit in the command packet, and (2) the fence counter is decremented responsive to the first response message including a second fence participant bit indicating fence participation, i.e., the decrement operation is conditional upon the presence and state of a fence participant bit in the response message.”
Reference Benisty discloses “responsive to the first response message including a second fence participant bit indicating fence participation [Para [0006]-[008], inclusion of metadata bits within completion entries; updating queue management state based upon completion entries; and carrying metadata within completion messages and updating queue management state based on those messages].”
Reference NEC Corp ‘245 discloses “In the following description, the values of addition and subtraction in each counter are described by taking “+1” and “−1” as examples, but are not limited to these values, and arbitrary values may be set.
The store counter increments the counter value by “+1” when the memory access control unit 14 issues a Store instruction to the memory, and increments the counter value by “−1” when receiving an Ack (Acknowledge) from the memory [See Description of Fig. 4].”
- For further details, please see below claims rejections under 35 USC 103. As such, the combination of references discloses the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9-13, 15, and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over King et al. (US 2009/0094388 A1) and Benisty (US 2020/0333975 A1) and NEC Corp ‘245 (JP 5811245 B1).
As per claim 1, King discloses a method comprising:
receiving a first packet at a command manager, the first packet comprising a first fence instruction and a first command for a first queue wherein the command manager is configured to enforce respective command execution policies for each of multiple queues according to respective fence instructions [Para [0017], The DMAC 104 includes an issue logic 110, a DMA command queue (DMAQ) 112, a request interface logic (RIL) 11, and a DMA completion logic (DCL) 13… ; Para [0018], The DCL 13 contains information as to whether the current list element is fenced. Preferably, this information is stored in the LM 118 and stores a table including indications of completion count, list, stall/fence, and finish.]. The DMAQ and DCL track per-command and per-queue state, including fencing;
responsive to the first fence instruction a first fence participant bit indicating fence participation, incrementing a fence counter and providing the first command to a command execution unit [Para [0025]. [0027], The stall/fence bit is set if the current list element is fenced; Para [0027], When a DMA request is issued out to the bus, the completion count in the completion logic is incremented by one.]. The stall/fence bit triggers logic; completion count is incremented as requests are issued;
and receiving, at a response queue, a first response message from the command execution unit based on the first command [Para [0027], Later, the bus will provide a completion for that DMA request, and the completion logic will decrement the completion count by one.] Completion responses are tracked and queued by the completion logic;
and decrementing the fence counter in coordination with receiving the first response message [Para 0027, Later, the bus will provide a completion for that DMA request, and the completion logic will decrement the completion count by one.]. Completion count is decremented on response, analogous to a fence counter.
King discloses the invention as detailed above in claim 1. King does not specifically teach responsive to the first response message including a second fence participant bit indicating fence participation as required by the claim.
Benisty discloses teach “responsive to the first response message including a second fence participant bit indicating fence participation [Para [0006]-[008], inclusion of metadata bits within completion entries; updating queue management state based upon completion entries; and carrying metadata within completion messages and updating queue management state based on those messages].”
NEC Corp ‘245 discloses “In the following description, the values of addition and subtraction in each counter are described by taking “+1” and “−1” as examples, but are not limited to these values, and arbitrary values may be set [Description of Fig. 4].
The store counter increments the counter value by “+1” when the memory access control unit 14 issues a Store instruction to the memory, and increments the counter value by “−1” when receiving an Ack (Acknowledge) from the memory.”
All references are in the same field of endeavor as they address management of queued operations and completion processing in high-performance communication or storage systems, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of King with the teachings of Benisty and NEC Corp ‘245 to decrement the outstanding fenced-operation count when a completion corresponding to a fenced operation is received. One of ordinary skill would have been motivated to implement the fence tracking using the well- known outstanding operation accounting techniques of King and the completion metadata mechanisms of Benisty and NEC Corp ‘245 in order to efficiently determine when all fenced operations have completed.
Motivation would improve queue management circuitry by including a fence identifying information within completion messages to identify which completions correspond to fenced operations. The combination would merely involve applying a known accounting technique involving incrementing upon issuance and decrementing upon completion to the known problem of tracking outstanding fenced operations and would have yielded predictable results.
As per claim 2, King discloses the method of claim 1, wherein providing the first command to the command execution unit includes providing the first command to a processor in the command manager, to a data mover, or to a processor outside of the command manager [Para 0020, The request interface logic 11 accesses the DMAQ 112 to retrieve a DMA command … This retrieved DMA command is then provided to the bus interface unit 106 via the connection 122]. It is noted that DMA commands are routed from the queue to execution units (bus interface).
As per claim 3, King discloses the method of claim 1, comprising: responsive to the first fence instruction indicating fence initiation: determining a counter value of the fence counter Para 0021, If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed … If the list elements are not fenced, the DMAC 104 does not have to wait for the prior DMA list element to be completed before starting to process the next list element.; responsive to the counter value indicating a different fenced operation is underway, stalling the first command [Para 0021, If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed … If the list elements are not fenced, the DMAC 104 does not have to wait for the prior DMA list element to be completed before starting to process the next list element.]; and responsive to the counter value indicating a new fenced operation can proceed, incrementing the fence counter and providing the first command to the command execution unit [Para 0021, If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed … If the list elements are not fenced, the DMAC 104 does not have to wait for the prior DMA list element to be completed before starting to process the next list element; Para 0022, Preferably, the LM 118 is configured to store a table that contains … completion count bits, a list bit, a stall/fence bit, and a finish bit.]. It is noted that Fence bit and completion count are used to stall or allow command execution.
As per claim 4, King discloses the method of claim 3, wherein the fence instruction comprises a message field including a first bit indicating fence participation and a second bit indicating fence initiation [Para 0022, Preferably, the LM 118 is configured to store a table that contains…; Para 0025, a stall/fence bit, and a finish bit.].
As per claim 5, King discloses the method of claim 1, comprising: responsive to the first fence instruction indicating fence initiation: determining a counter value of the fence counter, the fence counter corresponding to the first queue [Para 0021, The LM 118 is configured to store information used to determine whether the DMAC 104 should wait for the prior DMA list element to be completed before starting to process the next list element.]; responsive to the counter value indicating a different fenced operation is underway, stalling the first command [Para 0021, The LM 118 is configured to store information used to determine whether the DMAC 104 should wait for the prior DMA list element to be completed before starting to process the next list element.]; and responsive to the counter value indicating a new fenced operation can proceed, incrementing the fence counter corresponding to the first queue and providing the first command to a specified one of multiple available command execution units [Para 0023, completion count bits … incremented when requests are issued … decremented when … completes a request.]. It is noted that per-queue completion logic and stall/fence bits are used for execution control.
As per claim 6, King discloses the method of claim 1, wherein receiving the first packet at the command manager includes receiving the first packet at a memory-based queue established by a host application [Para 0019, The DMA command is temporarily held at the DMAQ 112. Preferably, the DMA command is initially stored in the local storage 108, and the MPU 102 is configured for sending a control signal to the DMAC 104 to inform the DMAC 104 that the DMA command is available from the local storage 108.]. It is noted that DMA commands are queued from host memory storage.
As per claim 9, King discloses the method of claim 1, comprising: receiving a second packet at the command manager, the second packet comprising a second fence instruction and a second command for the first queue [Para 0027, When a list element is fetched and enqueued, the list bit and stall/fence bit in the DCL 13 are updated.]; and responsive to information in the second fence instruction, selectively providing the second command to the command execution unit or stalling the second command [Para 0021, If the list elements are not fenced, the DMAC 104 does not have to wait … before starting to process the next list element.].
As per claim 10, King discloses the method of claim 9, comprising providing the second command to the command execution unit, without regard for a status of a previously-stalled command, when the second fence instruction indicates non-participation in a fence and the second fence instruction indicates non-initiation of a fence [Para 0016, If the current list element is not fenced, … the DMA engine can start processing the next list element before the current list element is completed on the bus.].
As per claim 11, King discloses the method of claim 1, comprising receiving a second packet at the command manager, the second packet comprising a second fence instruction and a first command for a second queue, wherein the command manager is configured to maintain separate fence policies for transactions from the first and second queues [Para 0028, The LM 218 is configured to store first and second tables (not shown) corresponding to the SPU 202 and the PU 204, respectively.].
As per claim 12, King discloses a system comprising: a memory device; and a command manager configured to enforce respective command execution policies for each of multiple queues according to respective command fence instructions wherein the command manager is further configured to:
receive a first packet comprising a first fence instruction and a first command for a first queue [Para 0017, The DMAC 104 includes an issue logic 110, a DMA command queue (DMAQ) 112, a request interface logic (RIL) 11, and a DMA completion logic (DCL) 13… ; Para 0018, The DCL 13 contains information as to whether the current list element is fenced. Preferably, this information is stored in the LM 118 and stores a table including indications of completion count, list, stall/fence, and finish.];
responsive to the first fence instruction including a first fence participating bit indicating fence participation, increment a fence counter and provide the first command to a memory controller of the memory device [Para [0025]. [0027], The stall/fence bit is set if the current list element is fenced; Para [0027], When a DMA request is issued out to the bus, the completion count in the completion logic is incremented by one.]. The stall/fence bit triggers logic; completion count is incremented as requests are issued; and
receive a first response message from the memory controller based on the first command [Para 0027, Later, the bus will provide a completion for that DMA request, and the completion logic will decrement the completion count by one.]; and
decrement the fence counter [Para 0027, Later, the bus will provide a completion for that DMA request, and the completion logic will decrement the completion count by one.]. It is noted the system includes memory device, command manager, fence logic, per-queue state, and response-based counter decrementing.
King discloses the invention as detailed above in claim 1. King does not specifically teach responsive to the first response message including a second fence participant bit indicating fence participation as required by the claim.
Benisty discloses teach responsive to the first response message including a second fence participant bit indicating fence participation [Para [0006]-[008], inclusion of metadata bits within completion entries; updating queue management state based upon completion entries; and carrying metadata within completion messages and updating queue management state based on those messages].
NEC Corp ‘245 discloses In the following description, the values of addition and subtraction in each counter are described by taking “+1” and “−1” as examples, but are not limited to these values, and arbitrary values may be set [Description of Fig. 4].
The store counter increments the counter value by “+1” when the memory access control unit 14 issues a Store instruction to the memory, and increments the counter value by “−1” when receiving an Ack (Acknowledge) from the memory.
Both references are in the same field of endeavor as they address management of queued operations and completion processing in high-performance communication or storage systems, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of King with the teachings of Benisty and NEC Corp ‘245 to decrement the outstanding fenced-operation count when a completion corresponding to a fenced operation is received. One of ordinary skill would have been motivated to implement the fence tracking using the well- known outstanding operation accounting techniques of King and the completion metadata mechanisms of Benisty and NEC Corp ‘245 in order to efficiently determine when all fenced operations have completed.
Motivation would improve queue management circuitry by including a fence identifying information within completion messages to identify which completions correspond to fenced operations. The combination would merely involve applying a known accounting technique involving incrementing upon issuance and decrementing upon completion to the known problem of tracking outstanding fenced operations and would have yielded predictable results.
As per claim 13, King discloses the system of claim 12, wherein the memory device comprises the command manager [Para 0018, 0022, The memory controller may include DMA completion logic (DCL) and local memory (LM) for tracking command status and fence/stall bits.]. It is noted the DCL and LM may be included within the memory controller/device.
As per claim 15, King discloses the system of claim 12, wherein the command manager is further configured to: responsive to the first fence instruction indicating fence initiation: determine a value of the fence counter, the value indicating whether the memory controller is occupied by a previous command [Para 0021, If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed … If the list elements are not fenced, the DMAC 104 does not have to wait for the prior DMA list element to be completed before starting to process the next list element.]; responsive to the value indicating the memory controller is occupied, stall the first command until the value indicates the memory controller is unoccupied [Para 0021, If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed … If the list elements are not fenced, the DMAC 104 does not have to wait for the prior DMA list element to be completed before starting to process the next list element]; and responsive to the value indicating the memory controller is unoccupied, increment the fence counter and provide the first command to the memory device [Para 0023, completion count bits … incremented when requests are issued … decremented when … completes a request.]. It is noted that the logic for stalling and proceeding based on fence state and counter is present.
As per claim 21, King discloses At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processor circuit of a memory system, cause the processor circuit to perform operations comprising:
receiving a first packet at a command manager, the first packet comprising a first fence instruction and a first command for a first queue wherein the command manager is configured to enforce respective command execution policies for each of multiple queues according to respective fence instructions [Para [0017], The DMAC 104 includes an issue logic 110, a DMA command queue (DMAQ) 112, a request interface logic (RIL) 11, and a DMA completion logic (DCL) 13… ; Para [0018], The DCL 13 contains information as to whether the current list element is fenced. Preferably, this information is stored in the LM 118 and stores a table including indications of completion count, list, stall/fence, and finish.]. The DMAQ and DCL track per-command and per-queue state, including fencing;
responsive to the first fence instruction a first fence participant bit indicating fence participation, incrementing a fence counter and providing the first command to a command execution unit [Para [0025]. [0027], The stall/fence bit is set if the current list element is fenced; Para [0027], When a DMA request is issued out to the bus, the completion count in the completion logic is incremented by one.]. The stall/fence bit triggers logic; completion count is incremented as requests are issued;
and receiving, at a response queue, a first response message from the command execution unit based on the first command [Para [0027], Later, the bus will provide a completion for that DMA request, and the completion logic will decrement the completion count by one.]. Completion responses are tracked and queued by the completion logic;
and decrementing the fence counter in coordination with receiving the first response message [Para 0027, Later, the bus will provide a completion for that DMA request, and the completion logic will decrement the completion count by one.]. Completion count is decremented on response, analogous to a fence counter.
King discloses the invention as detailed above in claim 1. King does not specifically teach responsive to the first response message including a second fence participant bit indicating fence participation as required by the claim.
Benisty discloses teach responsive to the first response message including a second fence participant bit indicating fence participation [Para [0006]-[008], inclusion of metadata bits within completion entries; updating queue management state based upon completion entries; and carrying metadata within completion messages and updating queue management state based on those messages].
NEC Corp ‘245 discloses In the following description, the values of addition and subtraction in each counter are described by taking “+1” and “−1” as examples, but are not limited to these values, and arbitrary values may be set [Description of Fig. 4].
The store counter increments the counter value by “+1” when the memory access control unit 14 issues a Store instruction to the memory, and increments the counter value by “−1” when receiving an Ack (Acknowledge) from the memory.
Both references are in the same field of endeavor as they address management of queued operations and completion processing in high-performance communication or storage systems, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of King with the teachings of Benisty and NEC Corp ‘245 to decrement the outstanding fenced-operation count when a completion corresponding to a fenced operation is received. One of ordinary skill would have been motivated to implement the fence tracking using the well- known outstanding operation accounting techniques of King and the completion metadata mechanisms of Benisty and NEC Corp ‘245 in order to efficiently determine when all fenced operations have completed.
Motivation would improve queue management circuitry by including a fence identifying information within completion messages to identify which completions correspond to fenced operations. The combination would merely involve applying a known accounting technique involving incrementing upon issuance and decrementing upon completion to the known problem of tracking outstanding fenced operations and would have yielded predictable results.
As per claim 22, King discloses The non-transitory machine-readable storage medium of claim 21, wherein the operations further comprise: responsive to a fence initiation instruction in a second packet: determining a counter value of the fence counter [Para [0021], “If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed …”]; and
responsive to the counter value indicating a fenced operation is underway, withholding a command from the second packet from the command execution unit [Para [0021], “If list elements of the list DMA command are fenced, then the DMAC 104 has to wait for the prior list DMA command to be completed …”]. Withholding/stalling commands based on fence state is described.
As per claim 23, King discloses The non-transitory machine-readable storage medium of claim 22, wherein the operations further comprise: receiving a third packet comprising a third fence instruction that does not include a fence participant bit set to indicate fence participation and does not include a fence initiator bit set to indicate fence initiation [Para [0016], “If the current list element is not fenced, … the DMA engine can start processing the next list element before the current list element is completed on the bus.”]; and
providing a third command from the third packet to the command execution unit without regard to the counter value of the fence counter [Para [0016], “If the current list element is not fenced, … the DMA engine can start processing the next list element before the current list element is completed on the bus.”]. Non-fenced elements are processed immediately, regardless of other fence states.
As per claim 24, King discloses The non-transitory machine-readable storage medium of claim 21, wherein the fence counter is a first fence counter corresponding to the first queue [Para [0028], “The LM 218 is configured to store first and second tables (not shown) corresponding to the SPU 202 and the PU 204, respectively.”]; and wherein the operations further comprise: receiving a fourth packet comprising a fourth fence instruction and a fourth command for a second queue different from the first queue [Para [0028], “The LM 218 is configured to store first and second tables (not shown) corresponding to the SPU 202 and the PU 204, respectively.”];
responsive to the fourth fence instruction including a fence participant bit indicating fence participation, incrementing a second fence counter corresponding to the second queue [Para [0028], “The LM 218 is configured to store first and second tables (not shown) corresponding to the SPU 202 and the PU 204, respectively.”]; and providing the fourth command to the command execution unit without regard to a counter value of the first fence counter, wherein the command manager maintains independent fence policies for the first queue and the second queue using the first fence counter and the second fence counter, respectively [Para [0028], “The LM 218 is configured to store first and second tables (not shown) corresponding to the SPU 202 and the PU 204, respectively.”]. Per-queue (per-processor) fence/state tables are maintained; independent counters for each queue.
As per claim 25, Benisty discloses The non-transitory machine-readable storage medium of claim 21, wherein: providing the first command to the command execution unit includes associating a transaction identifier with the first command [Para [0052], “The completion entry 500 contains data for writing (or posting) a completed command to a designated completion queue (CQ) on the host device (such as one of the completion queues of FIG. 4). As shown in FIG. 5, completion entry 500 includes … a command identifier field 514.”]; and
receiving the first response message includes receiving the transaction identifier with the first response message to correlate the first response message with the first command [Para [0052], “The completion entry 500 contains data for writing (or posting) a completed command to a designated completion queue (CQ) on the host device (such as one of the completion queues of FIG. 4). As shown in FIG. 5, completion entry 500 includes … a command identifier field 514.”]. Describes command identifier field in completion entries, which can be used for correlation of commands and responses.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 and 14 is/are rejected under 35 U.S.C. 103 as being obvious over King et al., (US 2009/0094388 A1) and Benisty (US 2020/0333975) and NEC Corp ‘245 (JP 5811245 B1) and Das Sharma (USPGPub 2021/0240655 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
As per claim 7, King discloses the method of claim 1, wherein providing the first command to the command execution unit includes communicating the first command from a host device to an accelerator device using a compute express link (CXL) interconnect [Para 0019, The MPU 102 generates a DMA command, which is transferred to the DMAC 104 via the connection 120.].
King describes transfer from host to DMA controller but does not mention CXL specifically.
Das Sharma discloses a host device to an accelerator device using a compute express link (CXL) interconnect [Para 0052-0061, 0064].
King, Benisty, NEC Corp ‘245 and Das Sharma are in the same field of endeavor and they are both in the use of interconnect for memory access commands art, and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of King, Benisty, NEC Corp ‘245 with the teaching of Das Sharma in order to allow resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages.
Modification would have provided an improved, high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate data center performance and maintain memory coherency between the CPU memory space and memory on attached devices as taught by Das Sharma (Para 0052).
As per claim 14, King discloses the system of claim 13, wherein the command manager is coupled to the memory controller using a compute express link (CXL) interconnect [Para 0017, The DMAC 104 is coupled to the bus interface unit 106 via a connection 122]. The claim is rejected as per the rationale used in claim 7 above.
As per claim 8, King discloses the claimed invention as detailed above for claim 1. King does not specifically teach providing the first command to the command execution unit includes using an unordered interconnect that provides respective transaction identifiers (TID) to command and response message pairs, including a first TID for a first pair comprising the first command and the first response message as recited in claim 8.
Das Sharma discloses the method of claim 1, wherein providing the first command to the command execution unit includes using an unordered interconnect that provides respective transaction identifiers (TID) to command and response message pairs, including a first TID for a first pair comprising the first command and the first response message [Para 0035-0039, describes TIDs for tracking transactions and relaxed ordering rules].
King, Benisty, NEC Corp ‘245 and Das Sharma are in the same field of endeavor and they are both in the use of interconnect for memory access commands art, and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of King, Benisty, NEC Corp ‘245 with the teaching of Das Sharma in order to allow resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages.
Modification would have provided an improved memory coherency between the CPU memory space and memory on attached devices as taught by Das Sharma (Para 0052).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shahar (US-20210081207-A1) discloses “…the first dependent WR including a fencing indication indicating that the first dependent WR should not be executed until the first controlling WR has completed…” (Para [0004]) and “…the executing entity checking a completion queue (CQ) in the physical memory to determine whether the CQ includes an entry indicating that the first controlling WR has completed.” (Para [0008]).
Balkan (US-20140181349-A1) discloses “the control logic of the bridge may include a pair of counters for each source in the SoC. The pair of counters may include a read counter and a write counter for a given source. When a read transaction of the given source is received and processed by the bridge, the corresponding read counter may be incremented, and when a response to the read transaction is received, then the read counter may be decremented. Similarly, when a write transaction generated by a given source is received and processed by the bridge, the corresponding write counter may be incremented, and when a response to the write transaction is received, then the write counter may be decremented [Para [0008]).
Stracovsky (US-6587894-B1) describes “The queues and controller unit 2010 also transfers the issued element from the command queue into the data queue as well as removing it from the command queue after the command was issued. The queues and controller unit 2010 also removes data elements from the data queue after the access to the memory has been completed.” (Para [137]).
Dinkjian (US-20140223115-A1) describes “As an entry is selected for processing from queue 106 and queue 108, the status bit for the entry is marked as ‘done’.” (Para [0035])“decrementing the entry queue counter for the selected event queue…” (Para [0096]).
ZALTSMAN (WO-2014031387-A1) describes receiving commands from multiple queues and enforcing execution order and collecting acknowledgements after execution.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
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June 24, 2026
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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