DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this application.
Information Disclosure Statement
The IDS filed on 09/13/2024 has not been considered since an English translation of the written opinion mailed on May 30, 2023 has not been provided.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1:
Lines 3-4 recite “performing optimization of a layout address of subroutines” and it is unclear if only one layout address of one of the subroutines is being optimized or if each layout address of each subroutine is being optimized.
Line 4 recites “subroutines” and lines 4-5 recite “a plurality of subroutines” and it is unclear what the difference is.
As per claim 10:
Line 6 recites “the subroutine” but it is unclear what this refers to since there are a plurality of subroutines.
Line 11 recites “imaging the layout address” but in line 6 recites “changing a layout address” so it is unclear if the imaging is done on the layout address or the changed layout address.
Claims 2-8 are dependent claims of claim 1, and fail to resolve the deficiencies of claim 1, so they are rejected for the same reasons.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non- statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because it is directed to software per se.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashemi et al. (US 20200160150 A1 hereinafter Hashemi).
As per claim 1, Hashemi teaches an information processing method to be executed by an information processing device, the method comprising performing optimization of a layout address of subroutines in an executable body including a plurality of subroutines, based on a learning result obtained by machine learning ([0052] The recurrent neural network systems described herein can also be used to optimize cache replacement policies; [0046] But because local cache is also of limited size, the computing system can store only a small subset of main memory in local cache at any given time. Consequently, the computing system 400 can advantageously predict a subset of future memory access addresses and store data from those addresses in local cache. If the computing system makes accurate predictions, the computing system can execute the computer program instructions faster; [0044] Typically, a given computer program instruction specifies an operation, e.g., load, store, add, subtract, nor, branch, etc., one or more source registers, and a destination register. The computing system 400 performs the specified operation on the data stored in the source registers and stores the result in the destination register. For example, a computer program instruction might specify that data stored in register A should be added to data stored in register B and that the result should be stored in register C. [0045] Generally, computing systems have a limited number of local registers, so data to be operated on is loaded into those local registers only when it is needed. But fetching data from memory is time-consuming and slows execution of computer programs. One solution to this problem is predicting data that will be operated on in the future, pre-fetching that data, and storing it in faster local memory such as a local cache 43).
As per claim 8, Hashemi teaches the information processing method according to claim 1, wherein the optimization includes optimizing the layout address for each system or each mode in which the executable body is executed ([0052] The recurrent neural network systems described herein can also be used to optimize cache replacement policies; [0046] But because local cache is also of limited size, the computing system can store only a small subset of main memory in local cache at any given time. Consequently, the computing system 400 can advantageously predict a subset of future memory access addresses and store data from those addresses in local cache. If the computing system makes accurate predictions, the computing system can execute the computer program instructions faster; [0044] Typically, a given computer program instruction specifies an operation, e.g., load, store, add, subtract, nor, branch, etc., one or more source registers, and a destination register. The computing system 400 performs the specified operation on the data stored in the source registers and stores the result in the destination register. For example, a computer program instruction might specify that data stored in register A should be added to data stored in register B and that the result should be stored in register C. [0045] Generally, computing systems have a limited number of local registers, so data to be operated on is loaded into those local registers only when it is needed. But fetching data from memory is time-consuming and slows execution of computer programs. One solution to this problem is predicting data that will be operated on in the future, pre-fetching that data, and storing it in faster local memory such as a local cache 43; [0040] By pre-fetching data from main memory and storing it in faster local cache before it is needed, computing systems can reduce the run time of computer programs. Recurrent neural networks can be used to predict data that should be pre-fetched.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hashemi in view of Gottin et al. (US 20210374523 A1 hereinafter Gottin).
As per claim 2, Hashemi teaches the information processing method according to claim 1.
Hashemi fails to teach further comprising generating a pair of an image and an evaluation score for the image, the image having been obtained by imaging the layout address based on number of times of executions on the layout address at the time of execution of the executable body, and performing the machine learning using a plurality of the pairs as a dataset, wherein the optimization includes optimizing the layout address using the learning result obtained by performing the machine learning.
However, Gottin teaches further comprising generating a pair of an image and an evaluation score for the image, the image having been obtained by imaging the layout address based on number of times of executions on the layout address at the time of execution of the executable body, and performing the machine learning using a plurality of the pairs as a dataset, wherein the optimization includes optimizing the layout address using the learning result obtained by performing the machine learning ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected. FIG. 3 (top graph) shows an example collection of raw trace (disk access IO) data 300, in which each row corresponds to an address in the disk, and each data point corresponds to a read or write operation in the address across time. The raw disc access operations are aggregated 305 to form an aggregated state index 310. The aggregate state index is then engineered to emphasize features of interest to form a composite state index 315; [0045] FIG. 4 is a functional block diagram showing an example process of creating a composite state index 315. As shown in FIG. 4, raw IO trace information on cache 118 is collected over time (block 400). To condense this raw trace information, in some embodiments the raw IO trace information is aggregated (block 405). For example, in some embodiments the universe of possible disk addresses is divided into a discrete set of address ranges S.sub.t[1]-S.sub.t[h] where h is equal to the number of bins. IO operations on each discrete address range are summed over a lookback period 320 to form an aggregated state vector (block 410) for a time instant S.sub.t. The aggregate state index 330 shown in the bottom graph of FIG. 3 is an index of the state vectors over time; [0088] FIGS. 9-11 are graphs showing experimental results of using a trained reinforcement learning process to dynamically tune cache policy parameters, according to some embodiments. These graphs show application of a DQN-agent for optimization of the look-ahead and α parameters from a look-ahead-LRU algorithm, which was simulated using actual trace data captured from a storage system; [0097] The methods described herein may be implemented as software configured to be executed in control logic).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Hashemi with the teachings of Gottin to use reinforcement learning to optimize cache policy (see Gottin [0083] The advantage of using a DQN-agent is that the DQN-agent learns during the execution of the cache policy).
As per claim 3, Hashemi and Gottin teach the information processing method according to claim 2. Gottin teaches further comprising performing execution of trace processing at a time of execution of the executable body including generation of the pair, wherein the execution of trace processing includes calculation of the evaluation score based on an execution time length or power consumption of the executable body ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected. FIG. 3 (top graph) shows an example collection of raw trace (disk access IO) data 300, in which each row corresponds to an address in the disk, and each data point corresponds to a read or write operation in the address across time. The raw disc access operations are aggregated 305 to form an aggregated state index 310. The aggregate state index is then engineered to emphasize features of interest to form a composite state index 315; [0045] FIG. 4 is a functional block diagram showing an example process of creating a composite state index 315. As shown in FIG. 4, raw IO trace information on cache 118 is collected over time (block 400). To condense this raw trace information, in some embodiments the raw IO trace information is aggregated (block 405). For example, in some embodiments the universe of possible disk addresses is divided into a discrete set of address ranges S.sub.t[1]-S.sub.t[h] where h is equal to the number of bins. IO operations on each discrete address range are summed over a lookback period 320 to form an aggregated state vector (block 410) for a time instant S.sub.t. The aggregate state index 330 shown in the bottom graph of FIG. 3 is an index of the state vectors over time.).
As per claim 9, it is a program claim of claim 1, so it is rejected for similar reasons.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hashemi and Gottin, as applied to claim 3 above, in view of Munoz et al. (US 20240144030 A1 hereinafter Munoz).
As per claim 4, Hashemi and Gottin teach the information processing method according to claim 3. Gottin teaches wherein the execution of trace processing includes calculation of the evaluation score ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected. FIG. 3 (top graph) shows an example collection of raw trace (disk access IO) data 300, in which each row corresponds to an address in the disk, and each data point corresponds to a read or write operation in the address across time. The raw disc access operations are aggregated 305 to form an aggregated state index 310. The aggregate state index is then engineered to emphasize features of interest to form a composite state index 315).
Hashemi and Gottin fail to teach calculation of the evaluation score such that the shorter the execution time length, the larger the value will be.
However, Munoz teaches calculation of the evaluation score such that the shorter the execution time length, the larger the value will be ([0086] higher relative latency values (e.g., values greater than one) represent improved latency (e.g., a shorter amount of time to execute the model).).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Hashemi and Gottin with the teachings of Munoz to easily illustrate latency (see Munoz [0086] Each of these latency values are provided for purposes of illustration and contrast).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hashemi and Gottin, as applied to claim 3 above, in view of Yamato et al. (US 20240338256 A1 hereinafter Yamato).
As per claim 5, Hashemi and Gottin teach the information processing method according to claim 3. Gottin teaches wherein the execution of trace processing includes calculation of the evaluation score ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected. FIG. 3 (top graph) shows an example collection of raw trace (disk access IO) data 300, in which each row corresponds to an address in the disk, and each data point corresponds to a read or write operation in the address across time. The raw disc access operations are aggregated 305 to form an aggregated state index 310. The aggregate state index is then engineered to emphasize features of interest to form a composite state index 315).
Hashemi and Gottin fail to teach calculation of the evaluation score such that the lower the power consumption, the larger the value will be.
However, Yamato teaches calculation of the evaluation score such that the lower the power consumption, the larger the value will be ([0462] the evaluation formula may be set such that the shorter the processing time and the lower the power consumption, the higher the score).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Hashemi and Gottin with the teachings of Yamato to improve performance (see Yamato [0023] According to the present invention, performance can be improved).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hashemi and Gottin, as applied to claim 3, in view of Tachibana (US 6691080 B1).
As per claim 6, Hashemi and Gottin teach the information processing method according to claim 3. Gottin teaches wherein the execution of trace processing includes adjustment of a size ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected; [0065] For example, assume that a given cache system is using a segmented least recently used cache policy, where the parameter α corresponds to the ratio between the sizes of the probatory and protected regions; [0037] As used herein, the term “SLRU” is used to refer to Segmented LRU, a variant of an LRU cache wherein the cache is divided in two regions: probatory and protected; [0091] As shown in the middle graphic 910 of FIG. 9, the DQN agent converged on a cache segmentation value of α=0.8 (915) that is a local optimal for the ratio between the sizes of the probatory and protected regions; [0085] Once the action has been selected, the action is applied to the cache 118 by causing the cache parameter adjustment module 250 to take the selected action 630 on the cache 118 to adjust the cache parameter).
Hashemi and Gottin fail to teach adjustment of a size of the image based on a size of cache memory included in the information processing device.
However, Tachibana teaches adjustment of a size of the image based on a size of cache memory included in the information processing device (Col. 5 lines 34-36 graphs showing the cache hit ratio, execution time, and area which change depending on the cache size).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Hashemi and Gottin with the teachings of Tachibana to optimize the system (see Tachibana Col. 17 lines 59-60 the system can be optimized.).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hashemi and Gottin, as applied to claim 3 above, in view of Goss et al. (US 20220147279 A1 hereinafter Goss).
As per claim 7, Hashemi and Gottin teach the information processing method according to claim 3. Gottin teaches wherein the execution of trace processing includes generation of the image ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected. FIG. 3 (top graph) shows an example collection of raw trace (disk access IO) data 300, in which each row corresponds to an address in the disk, and each data point corresponds to a read or write operation in the address across time. The raw disc access operations are aggregated 305 to form an aggregated state index 310. The aggregate state index is then engineered to emphasize features of interest to form a composite state index 315).
Hashemi and Gottin fail to teach generation of the image as a heatmap that changes in luminance according to number of times of instructions executed for an address of main memory included in the information processing device.
However, Goss teaches generation of the image as a heatmap that changes in luminance according to number of times of instructions executed for an address of main memory included in the information processing device ([0120] Various embodiments of the heat module 330 track and map the frequency of data accesses to various memory cells to understand where data is most frequently read, written, updated, error corrected, and moved. Such a map can complement a heat map and can be at a different granularity. For example, activity frequency map may have a granularity that tracks each physical block address while a heat map can have a granularity of per plane or die of memory. The ability to alter the granularity in which memory cell activity frequency and generated heat are tracked allows the heat module 330 to maintain a balance of the processing resources used to track activity to memory with the accuracy of understanding how much, and where, heat is present.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Hashemi and Gottin with the teachings of Goss to optimize performance (see Goss [0116] The ranking of namespaces allows the heat module to generate and adjust cooling strategy policy actions that provide the greatest opportunity to satisfy performance expectations with mitigated accumulations of heat in view of current and future predicted namespace workloads.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20130061240 A1 hereinafter Yan) in view of Gottin.
As per claim 10, Yan teaches a method to be executed by a device, the method comprising: executing a link of a plurality of execution bodies, each of the executable bodies including a plurality of subroutines, the execution of the link performed while optionally changing a layout address of the subroutine in the executable body; and executing each of the plurality of execution bodies generated by executing the link ([0027] In one embodiment, a linker may generate a final CPU executable; [0048] the CPU linker 690 may generate CPU executables 695; [0048] the GPU linker 640 may generate GPU executables 645; [0028] The run time library may use the start symbol to identify the start address of the special section .VtGPU. After identifying the section start address, the GPU side linker/loader may adjust the GPU executable base address such that the GPU vtable section may also reside at the same address; [0027] The linker may collect GPU compiler generated vtable codes at one contiguous section in the CPU executable; [0023] the first member functions that are executed only by the GPU but that may be called by the CPU are annotated with a first annotation tag. Also, the second member functions that may be executed only by the CPU ).
Yan fails to teach a learning method to be executed by a learning device, the learning method comprising: generating a pair of an image and an evaluation score for the image, the image having been obtained by imaging the layout address based on number of times of executions on the layout address at a time of execution, and performing machine learning using a plurality of the pairs as a dataset.
However, Gottin teaches a learning method to be executed by a learning device, the learning method comprising: generating a pair of an image and an evaluation score for the image, the image having been obtained by imaging the layout address based on number of times of executions on the layout address at a time of execution, and performing machine learning using a plurality of the pairs as a dataset ([0044] As shown in FIG. 4, in some embodiments, the input/output (IO) raw trace data 300 describing input/output actions on the cache is collected. FIG. 3 (top graph) shows an example collection of raw trace (disk access IO) data 300, in which each row corresponds to an address in the disk, and each data point corresponds to a read or write operation in the address across time. The raw disc access operations are aggregated 305 to form an aggregated state index 310. The aggregate state index is then engineered to emphasize features of interest to form a composite state index 315; [0045] FIG. 4 is a functional block diagram showing an example process of creating a composite state index 315. As shown in FIG. 4, raw IO trace information on cache 118 is collected over time (block 400). To condense this raw trace information, in some embodiments the raw IO trace information is aggregated (block 405). For example, in some embodiments the universe of possible disk addresses is divided into a discrete set of address ranges S.sub.t[1]-S.sub.t[h] where h is equal to the number of bins. IO operations on each discrete address range are summed over a lookback period 320 to form an aggregated state vector (block 410) for a time instant S.sub.t. The aggregate state index 330 shown in the bottom graph of FIG. 3 is an index of the state vectors over time; [0088] FIGS. 9-11 are graphs showing experimental results of using a trained reinforcement learning process to dynamically tune cache policy parameters, according to some embodiments. These graphs show application of a DQN-agent for optimization of the look-ahead and α parameters from a look-ahead-LRU algorithm, which was simulated using actual trace data captured from a storage system; [0097] The methods described herein may be implemented as software configured to be executed in control logic).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Yan with the teachings of Gottin to use reinforcement learning to optimize cache policy (see Gottin [0083] The advantage of using a DQN-agent is that the DQN-agent learns during the execution of the cache policy).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSING CHUN LIN whose telephone number is (571)272-8522. The examiner can normally be reached Mon - Fri 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.L./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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