Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See MPEP § 606.01.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: reversal processing unit, encoding unit, flag setting unit, reversal control unit, decoding unit and geometry construction unit in claims 1-12 and 14-19.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 6-9, 12-15 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugio et al. (U.S. 2020/0366941), hereinafter Sugio in view of Cheon et al. (U.S. 2013/0195202), hereinafter Cheon.
Regarding claims 1 and 13, Sugio discloses an information processing device comprising:
a reversal processing unit that performs reversal processing on a reversal range in a tree structure representing a geometry of point cloud (Sugio [1012], [1009]-[1010] and figs. 139-141); and
an encoding unit that encodes geometry data having the tree structure having been subjected to the reversal processing (Sugio [1061] and fig. 141), wherein
the reversal range includes a reversal root node and a descendant node of the reversal root node and is a node range to be subjected to the reversal processing (Sugio figs. 139-140), and
the reversal processing is processing that reverses a bit pattern included in the reversal range (Sugio [1012]) and associates a bit pattern of a non-leaf node included in the reversal range with a bit pattern of a child node (Sugio figs. 139-140).
Sugio does not explicitly disclose the reversal processing is processing that reverses a bit pattern of a leaf node included in the reversal range and associates a bit pattern of a non-leaf node included in the reversal range with a bit pattern of a child node.
However, Cheon teaches the reversal processing is processing that reverses a bit pattern of a leaf node included in the reversal range and associates a bit pattern of a non-leaf node included in the reversal range with a bit pattern of a child node (Cheon [0267] and fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sugio’s device with the missing limitations as taught by Cheon to improve encoding efficiency as a result of the reversal (Cheon [0267]).
As shown above, all of the limitations are known, they can be applied to a known device such as a processor to yield a predictable result of improving coding efficiency.
Regarding claim 6, Sugio in view of Cheon teaches the information processing device according to claim 1, further comprising a reversal control unit that controls whether to perform the reversal processing (Sugio [1061] and [1012]).
Regarding claim 7, Sugio in view of Cheon teaches the information processing device according to claim 6, wherein the reversal control unit controls whether to perform the reversal processing, on a basis of encoding efficiency of encoded data of the geometry data (Sugio [0008] and Cheon [0267]).
The same motivation for claim 1 applies to claim 7.
Regarding claim 8, Sugio in view of Cheon teaches the information processing device according to claim 6, wherein the reversal control unit controls whether to perform the reversal processing, on a basis of the number of points in the reversal range (Sugio figs. 139-140 and Cheon [0267]).
The same motivation for claim 1 applies to claim 8.
Regarding claim 9, Sugio in view of Cheon teaches the information processing device according to claim 6, wherein the reversal control unit controls whether to perform the reversal processing, on a basis of the number of nodes deleted by the reversal processing (Sugio figs. 139-140 and Cheon [0267]).
The same motivation for claim 1 applies to claim 9.
Regarding claim 12, Sugio in view of Cheon teaches the information processing device according to claim 1, wherein the reversal processing unit performs the reversal processing after generation of a node in a region including no points in the reversal range (Sugio [1012] and figs. 139-140).
Regarding claims 14 and 20, Sugio in view of Cheon teaches an information processing device comprising:
a decoding unit (Sugio [1072]) that decodes encoded data of geometry data of point cloud (Sugio fig. 142), and
a reversal processing unit that performs reversal processing on a reversal range in a tree structure representing a geometry of the point cloud, the geometry being included in the geometry data obtained by decoding (Sugio [1012], [1009]-[1010], figs. 139-140 and 142), wherein
the reversal range includes a reversal root node and a descendant node of the reversal root node and is a node range to be subjected to the reversal processing (Sugio figs. 139-140), and
the reversal processing is processing that reverses a bit pattern of a leaf node included in the reversal range (Sugio [1012] and Cheon [0267] and fig. 11) and associates a bit pattern of a non-leaf node included in the reversal range with a bit pattern of a child node (Sugio figs. 139-140).
The same motivation for claim 1 applies to claims 14 and 20.
Regarding claim 15, Sugio in view of Cheon teaches the information processing device according to claim 14, further comprising a reversal control unit that controls whether to perform the reversal processing (Sugio [1072] and [1012]).
Regarding claim 19, Sugio in view of Cheon teaches the information processing device according to claim 14, further comprising a geometry construction unit that constructs a geometry of a three-dimensional space by using the tree structure having been subjected to the reversal processing (Sugio [1023] and fig. 142).
Claim(s) 2-5 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugio in view of Cheon as applied to claim 1 above, and further in view of Shinbashi et al. (U.S. 2017/0293513), hereinafter Shinbashi.
Regarding claim 2, Sugio in view of Cheon teaches the information processing device according to claim 1, further comprising a flag setting unit (Sugio [0541] and [1061]) that sets a flag indicating whether to perform data processing (Sugio [0558]).
Sugio does not explicitly disclose setting a bit reversal flag for the reversal root node of the reversal range, the bit reversal flag indicating whether to perform the reversal processing on the reversal range.
However, Shinbashi teaches setting a bit reversal flag for the reversal root node of the reversal range, the bit reversal flag indicating whether to perform the reversal processing on the reversal range (Shinbashi [0082] and fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device taught by Sugio in view of Cheon with the missing limitations as taught by Shinbashi to make it easier for devices to determine whether to perform reversal processing (Shinbashi [0082]).
As shown above, all of the limitations are known, they can be applied to a known device such as a processor to yield a predictable result of improving coding efficiency.
Regarding claim 3, Sugio in view of Cheon and Shinbashi teaches the information processing device according to claim 2, wherein the flag setting unit sets bit reversal flags independently for all nodes of the tree structure (Sugio [1012], figs. 139-140 and Shinbashi fig. 5).
The same motivation for claim 2 applies to claim 3.
Regarding claim 4, Sugio in view of Cheon and Shinbashi teaches the information processing device according to claim 2, wherein the flag setting unit sets one of the bit reversal flags for ascendant/descent nodes of the tree structure, and the ascendant/descent nodes are nodes including nodes having a parent-child relationship in the tree structure (Sugio [1012], figs. 139-140 and Shinbashi fig. 5).
The same motivation for claim 2 applies to claim 4.
Regarding claim 5, Sugio in view of Cheon and Shinbashi teaches the information processing device according to claim 2, wherein the flag setting unit sets one of the bit reversal flags for an entirety of the tree structure (Sugio [1012], figs. 139-140 and Shinbashi fig. 5).
Regarding claim 16, Sugio in view of Cheon and Shinbashi teaches the information processing device according to claim 15, wherein the reversal control unit controls whether to perform the reversal processing on a basis of bit reversal flags indicating whether to perform the reversal processing on the reversal range, the bit reversal flags being set for all the nodes of the tree structure (Sugio [1012], figs. 139-140 and Shinbashi fig. 5).
The same motivation for claims 1 and 2 applies to claim 16.
Regarding claim 17, Sugio in view of Cheon and Shinbashi teaches the information processing device according to claim 15, wherein the reversal control unit controls whether to perform the reversal processing on a basis of one bit reversal flag indicating whether to perform the reversal processing on the reversal range, the one bit reversal flag being set for ascendant/descent nodes of the tree structure (Shinbashi fig. 5 and Sugio [1012], figs. 139-140).
The same motivation for claims 1 and 2 applies to claim 17.
Regarding claim 18, Sugio in view of Cheon and Shinbashi teaches the information processing device according to claim 15, wherein the reversal control unit controls whether to perform the reversal processing on a basis of one bit reversal flag indicating whether to perform the reversal processing on the reversal range, the one bit reversal flag being set for the overall tree structure (Shinbashi fig. 5 and Sugio [1012], figs. 139-140).
The same motivation for claims 1 and 2 applies to claim 18.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugio in view of Cheon as applied to claim 1 above, and further in view of Yano et al. (WO 2020/066680 A1), hereinafter Yano. An NPL English translation has been attached and referred to for citations below.
Regarding claim 10, Sugio in view of Cheon teaches the information processing device according to claim 1.
Sugio does not explicitly disclose wherein the reversal processing unit deletes a node of the bit pattern including only 0 after the reversal processing is performed.
However, Yano teaches, wherein the reversal processing unit deletes a node of the bit pattern including only 0 after the reversal processing is performed (Yano p. 3, 6 lines above <Octree encoding> section at the bottom of the page).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device taught by Sugio in view of Cheon with the missing limitations as taught by Yano to increase compression efficiency as a result of not needing to encode as much information (Yano p. 3, 2 lines above <Octree encoding> section).
As shown above, all of the limitations are known, they can be applied to a known device such as a processor to yield a predictable result of improving coding efficiency.
Regarding claim 11, Sugio in view of Cheon and Yano teaches the information processing device according to claim 10, wherein the reversal processing unit deletes the node of the bit pattern indicating sparse points after the reversal processing is performed (Yano p. 3).
The same motivation for claim 10 applies to claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW KWAN whose telephone number is (571)270-7073. The examiner can normally be reached Monday-Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chris Kelley can be reached at (571)272-7331. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW K KWAN/Primary Examiner, Art Unit 2482