DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2023/0197756 A1).
Claim 1, Lee teaches a solid-state imaging device (Fig. 1) comprising:
a pixel circuit configured to output a signal based on intensity of light received by a light receiving element (charges generated in response to light in each of pixels PX; paragraph 0032);
a pixel array in which the pixel circuit is arranged in a two-dimensional array in a first direction and a second direction intersecting the first direction (pixel array 10; Fig. 1);
a first signal line connected to the pixel circuit continuous in the second direction (column lines; paragraph 0028 and Fig. 1); and
a first signal processing circuit configured to perform signal processing on a signal from the pixel circuit output from a plurality of the signal lines (“readout circuit 22 may include a “correlated double sampler (CDS), an analog-to-digital converter (ADC), and the like;” paragraph 0028), wherein each of at least one transistor in the pixel circuit (transistor TR1 may be comprised of a three-dimensional transistor; paragraph 0092) and at least one transistor in the first signal processing circuit is a three-dimensional transistor (logic circuit 20 may include the readout circuit 22, paragraph 0027, TR_L1 may be transistors constituting the logic circuit 20 and may be comprised of a three-dimensional transistor; paragraphs 0090-0092).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Liaw (2021/0210603 A1).
Claim 3, Lee teaches the solid-state imaging device according to claim 1, but is silent regarding wherein a negative potential is applied to a well region of a plurality of the three-dimensional transistors.
Liaw teaches wherein a negative potential is applied to a well region of a plurality of the three-dimensional transistors (n-doped region 14 in FinFET transistors; paragraph 0019).
It would have been obvious to try a negative potential applied to a well region of the plurality of transistors since well regions are either positive or negative depending on the semiconductor circuitry design. It would further have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the n-type doped well of Liaw with the transistors of Lee in order to stabilize the well potential, facilitating uniform charge distribution throughout a memory array (see paragraph 0015 of Liaw).
Claim 16, Lee teaches a semiconductor device, the semiconductor device comprising:
a pixel circuit configured to output a signal based on intensity of light received by a light receiving element (charges generated in response to light in each of pixels PX; paragraph 0032);
a pixel array in which the pixel circuit is arranged in a two-dimensional array in a first direction and a second direction intersecting the first direction (pixel array 10; Fig. 1);
a signal line connected to the pixel circuit continuous in the second direction (column lines; paragraph 0028 and Fig. 1); and
a selector configured to select a signal from the pixel circuit output from a plurality of the signal lines (readout circuit acquires pixel signals from the pixels PX selected by row driver 21; paragraph 0032), wherein each of at least one transistor in the pixel circuit (transistor TR1 may be comprised of a three-dimensional transistor; paragraph 0092) and at least one transistor in the selector is a three-dimensional transistor (logic circuit 20 may include the readout circuit 22, paragraph 0027, TR_L1 may be transistors constituting the logic circuit 20 and may be comprised of a three-dimensional transistor; paragraphs 0090-0092),
but Lee is silent regarding a manufacturing method comprising:
forming the three-dimensional transistor in the pixel circuit and the three-dimensional transistor in the selector in a same step.
Liaw teaches wherein lithography and etching processes are used to form the fins of a transistor together in a single layer (paragraph 0023).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of lithography of Liaw with the circuitry of Lee in order to improve performance of the semiconductor device (see paragraph 0015 of Liaw).
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Murakami ’565 (US 2014/0240565 A1).
Claim 4, Lee teaches the solid-state imaging device according to claim 1, but is silent regarding: a first substrate on which at least the pixel circuit and the first signal processing circuit are formed; and
a second substrate on which at least a second signal processing circuit connected to the first signal processing circuit via a second signal line is formed, wherein the first substrate and the second substrate are stacked to be formed.
Murakami ’565 teaches a solid-state imaging device comprising a first substrate (upper chip 21; paragraph 0085) on which at least the pixel circuit and the first signal processing circuit are formed (a peripheral circuit, such as bias generation sub-circuit 201 is formed on the upper chip; see paragraph 0088 and Fig. 5); and
a second substrate (lower chip 22; paragraph 0085) on which at least a second signal processing circuit connected to the first signal processing circuit via a second signal line is formed, wherein the first substrate and the second substrate are stacked to be formed (bias generation sub-circuit 202 is integrated in the peripheral circuit 32-2 into lower chip 22; paragraph 0095).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the stacked image sensor of Murakami ’565 with the three-dimensional transistor circuits of Lee in order to reduce cost of manufacture of a solid-state imaging device (see paragraph 0011-0012 of Murakami ’565).
Claim 5, Lee further teaches wherein the three-dimensional transistor is formed in the first substrate (transistors TR1-TR4 of a pixel circuit are formed in a first lower chip CH_L1; paragraph 0074-0075).
Claim 6, Murakami ’565 further teaches wherein the first signal processing circuit includes:
a load transistor through which a current according to a bias voltage flows (see bias generation sub-circuit 201 comprising transistor 232 through which a reference voltage flows; see Fig. 6).
Claim 7, Murakami ’565 teaches the load transistor (transistor 232) but does not expressly disclose that the load transistor is formed by a three-dimensional transistor.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of the three-dimensional transistors of Lee with the load transistor of the prior art to reduce the physical size of a transistor vis-à-vis a more traditional planar transistor and to increase the density of transistors fitting on a substrate.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Murakami ’331 (US 2014/0160331 A1).
Claim 11, Lee teaches the solid-state imaging device according to claim 1, but is silent regarding wherein the first signal processing circuit includes:
a transistor that is connected to the first signal line and forms a differential pair that receives a reference signal and a signal output from the first signal line.
Murakami ’331 teaches wherein a signal processing circuit includes a transistor (differential pair transistor 112; paragraph 0092 and Fig. 3) that is connected to the first signal line (signal line 22-x; Fig. 3) and forms a differential pair that receives a reference signal and a signal output from the first signal line (differential pair transistors 111 and 112; paragraph 0093. Signal voltage Bx is input via capacitive element 117 into differential pair transistor 112; paragraph 0093).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of the differential amplifier of Murakami ’331 with that of Lee in order to reduce noise resulting from current fluctuation of an amplifying amplifier 9see paragraph 0014-0015 of Murakami ’331).
Claim 12, Murakami ’331 teaches the transistor forming the differential pair but does not expressly teach that the transistor is formed by the three-dimensional transistor.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of the three-dimensional transistors of Lee with the load transistor of the prior art to reduce the physical size of a transistor vis-à-vis a more traditional planar transistor and to increase the density of transistors fitting on a substrate.
Claim 13, Murakami ’331 further teaches a load transistor that is connected to a transistor forming the differential pair and through which a current according to a bias voltage flows (transistor 115 connected to transistor 112 through which Vbias flows; see Fig. 3).
Claim 14, Murakami ’331 teaches the load transistor (transistor 115) but does not expressly disclose that the load transistor is formed by a three-dimensional transistor.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of the three-dimensional transistors of Lee with the load transistor of the prior art to reduce the physical size of a transistor vis-à-vis a more traditional planar transistor and to increase the density of transistors fitting on a substrate.
Claim 15, Murakami ’331 teaches the transistor (transistor 170; Fig. 3) connected to a gate of the load transistor (transistor 115; Fig. 3), but does not expressly teach the transistor is formed by a three-dimensional transistor.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the teaching of the three-dimensional transistors of Lee with the load transistor of the prior art to reduce the physical size of a transistor vis-à-vis a more traditional planar transistor and to increase the density of transistors fitting on a substrate.
Allowable Subject Matter
Claims 2, 8-10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 attached.
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/CHIAWEI CHEN/Primary Examiner, Art Unit 2637
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