DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-7, 13-14, 17-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teng et al. ("An on-chip 2-d dft accelerator ultrasonic wavefront for convolutional neural networks." 2021 IEEE USNC-URSI Radio Science Meeting (Joint with AP-S Symposium). IEEE, 2021., “Teng”) in view of Patel et al. ("SonicFFT: A system architecture for ultrasonic-based FFT acceleration." 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2022., “Patel”).
Regarding claim 1, Teng discloses a two-dimensional discrete Fourier transform hardware accelerator (Fig. 1 illustrates a transmitter and receiver with NxN transducers array for 2D-DFT ultrasonic wavefront architecture) comprising:
an ultrasonic transmitter (Fig. 1 (TX)) comprising: an input data interface block configured to receive input and control signals (Fig. 1 (Data in) and (Input Buffer)([[pg. 1], real-time raw data from spatial domain is sent to serial-to-parallel converter to store data to the input buffer. Phase-locked loop generates carrier signal for data transmission through each transducer in the pixel array. Input buffer data is used to modulate the phase and amplitude of carrier signal so that a complex-valued signal is transmitted);
each transmitter pixel comprises a I path modulation block that is provided with a first set of quadrature phase carrier signals, and a Q path modulation block that is provided with a second set of quadrature phase carrier signals([pg. 1-2] in the TX chip, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission)
the array of transmitter pixels is configured to transmit to a lens provided between the ultrasonic transmitter and an ultrasonic receiver(Fig. 1 (lens))([pg. 1], FT operation can be obtained on the NxN input transducer array of the RX through diffraction physics on the ultrasonic wave propagation to the fused silica and lens), ultrasonic waves generated by the I and Q path modulation blocks based on the input signals and the first and second sets of quadrature phase carrier signals([pg. 1-2] in the TX chip, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission);
the ultrasonic receiver (Fig. 1 (RX) comprising:
an array of receiver pixels ([pg. 1] the received signal of each pixel is then demodulated through a carrier signal generated by the PLL block in the RX), whereby each receiver pixel comprises an IQ demodulator that is provided with a third and a fourth set of quadrature phase carrier signals([pg. 1-2] in the TX, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission. The same concept is applied to the demodulation in the RX), and whereby each receiver pixel is configured to use the IQ demodulator in each receiver pixel to down convert ultrasonic waves received from the lens to I and Q baseband signals based on the third and fourth sets of quadrature phase carrier signals ([pg. 1] A time division multiplexing method is applied for the RX analog-front-end so that a variable gain amplifier is used for each N column pixels. As the gain of the RX can be dynamically changed, the dynamic range of the analog-to-digital converter requirement can be relaxed to cover the RX sensitivity);
a plurality of analog baseband and analog-to-digital converter (ADC) pairs configured to convert the I and Q baseband signals received from the receiver pixels to digital representations (Fig. 1 illustrates N (I/Q RX AFE) and N (SAR ADC) corresponding to the NxN transducer array).
Teng fails to teach a memory module configured to receive and store input signals from the input data interface block and based on the control signals, to selectively provide the input signals to an array of transmitter pixels.
Patel teaches a memory module configured to receive and store input signals from the input data interface block and based on the control signals, to selectively provide the input signals to an array of transmitter pixels (Fig. 2 (Input Data Buffer) buffers incoming data from host CPU for transmit through the (Transmit Transducer Array))([pg. 2] transmit array is comprised of pixels)([pg. 3], SRAM based local memory buffers the incoming and outgoing data)
Accordingly, it would have been obvious to one having ordinary skill in the art to modify the hardware accelerator of Teng, to include the teachings of Patel, in order to have the input data buffer instructions stored locally to buffer input data transmitted from the central processing unit. Making this modification, where the memory module is configured to locally store input signals from an input data interface block, would only be a matter combining prior art elements according to known methods to yield predictable results. See MPEP 2141.III KSR Rational A.
The motivation in doing so is to provide a local memory that can reduce the latency and power consumption of the hardware accelerator to a negligible level (Patel, [pg. 4]).
Regarding claim 4, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng further teaches whereby each I path modulation block comprises:
a multiplexer configured to receive the first set of quadrature phase carrier signals and the input signal from the memory module ([pg. 1], input buffer data is used to modulate the phase and amplitude of the carrier signal so that a complex-valued signal is transmitted)([pg. 1] A time division multiplexing method is applied for the RX analog-front-end so that a variable gain amplifier is used for each N column pixels. As the gain of the RX can be dynamically changed, the dynamic range of the analog-to-digital converter requirement can be relaxed to cover the RX sensitivity);
an I-driver (Fig. 1 (I/Q Driver)) configured to generate a modulated signal based on the input signal and the first set of quadrature phase carrier signals received from the multiplexer([pg. 1-2] in the TX, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission);
and a transducer (Fig. 1 (AlN transducer)) configured to generate and transmit ultrasonic waves based on the modulated signal generated by the I-driver(Fig. 1 (I/Q Driver)([pg. 1], By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission).
Regarding claim 5, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng further teaches whereby each Q path modulation block comprises:
a multiplexer configured to receive the second set of quadrature phase carrier signals and the input signal from the memory module([pg. 1], input buffer data is used to modulate the phase and amplitude of the carrier signal so that a complex-valued signal is transmitted)([pg. 1] A time division multiplexing method is applied for the RX analog-front-end so that a variable gain amplifier is used for each N column pixels. As the gain of the RX can be dynamically changed, the dynamic range of the analog-to-digital converter requirement can be relaxed to cover the RX sensitivity);
a Q-driver (Fig. 1 (I/Q Driver) configured to generate a modulated signal based on the input signal and the second set of quadrature phase carrier signals received from the multiplexer([pg. 1-2] in the TX, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission);
and a transducer (Fig. 1 (AlN transducer)) configured to generate and transmit ultrasonic waves based on the modulated signal generated by the Q-driver(Fig. 1 (I/Q Driver)([pg. 1], By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission).
Regarding claim 6, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng further teaches
whereby each I path modulation block comprises: a multiplexer configured to receive the first set of quadrature phase carrier signals and the input signal from the memory module (Fig. 1 illustrates N x N(I/Q RX AFE)) ([pg. 1] A time division multiplexing method is applied for the RX analog-front-end);
a plurality of I-driver and transducer pairs(Fig. 1 illustrates N (I/Q Drivers) corresponding to the NxN (AlN trandsucers)
whereby each I-driver is configured to generate a modulated signal based on the input signal and the first set of quadrature phase carrier signals received from the multiplexer and each transducer is configured to generate and transmit ultrasonic waves based on the modulated signal generated by the I-driver([pg.1], input buffer data is used to modulate the phase an amplitude of carrier signals so that complex-valued signals are transmitted)([pg. 1-2] in the TX, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission).
Regarding claim 7, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng further teaches
whereby each Q path modulation block comprises: a multiplexer configured to receive the second set of quadrature phase carrier signals and the input signal from the memory module (Fig. 1 illustrates N x N(I/Q RX AFE)) ([pg. 1] A time division multiplexing method is applied for the RX analog-front-end);
a plurality of Q-driver and transducer pairs(Fig. 1 illustrates N (I/Q Drivers) corresponding to the NxN (AlN trandsucers)
whereby each Q-driver is configured to generate a modulated signal based on the input signal and the first set of quadrature phase carrier signals received from the multiplexer and each transducer is configured to generate and transmit ultrasonic waves based on the modulated signal generated by the Q-driver([pg.1], input buffer data is used to modulate the phase an amplitude of carrier signals so that complex-valued signals are transmitted)([pg. 1-2] in the TX, I and Q paths in each pixel are in quadrature phase with each other. By varying amplitude of the carrier signal in both paths and adding them together, complex signal with phase an amplitude modulations is formed for transmission)..
Regarding claim 13, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng further teaches whereby the ultrasonic waves received from the lens by the array of receiver pixels comprises Fourier transform waves formed when ultrasonic waves transmitted from the transmitter superimposed at the lens constructively and destructively (Implicit, [pg. 1], fourier transform operation can be obtained on the N x N input transducer array of the RX through diffraction physics on the ultrasonic wave propagation to the fused silica and lens.)([pg. 1], this architecture forms a 2D-DFT accelerator where N x N pixels array frame rate of input raw data are encoded in the TX and the resulted fourier transform operation is recovered as digital forms in the RX).
Regarding claim 14, the claim is a method claim corresponding to claim 1 and is therefore rejected for the same reasons.
Regarding claim 17, the claim is a method claim corresponding to claim 4 and is therefore rejected for the same reasons.
Regarding claim 18, the claim is a method claim corresponding to claim 5 and is therefore rejected for the same reasons.
Regarding claim 20, the claim is a system claim corresponding to claim 1 and is therefore rejected for the same reasons.
Allowable Subject Matter
Claims 2-3, 8-12, 15-16, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng, as modified in view of Patel fails to teach whereby the ultrasonic receiver further comprises:
Teng teaches a controller configured to delay the down conversion of the ultrasonic waves by the array of receiver pixels however Teng makes no recitation of delaying the down conversion of the ultrasonic waves by the array of receiver pixels by any propagation delay, let along the required diagonal propagation delay tpropDL.. Teng further makes no recitation of any length between transmitter and receiver pixels that would supply any implicit teaching of the limitation.).
Patel teaches a controller configured to delay the down conversion of the ultrasonic waves by the array of receiver pixels However Patel makes no recitation of any delay being applied to the conversion, let along the specific nature of the delay be applied based on the diagonal length between transmitter pixels and receiver pixels)
No other prior art teaches the required limitations either wholly or in part with sufficient motivation to combine.
Regarding claim 3, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1. Teng, as modified in view of Patel Fails to teach:
Teng teaches whereby the hardware accelerator the demodulation in the RX chip. However Teng fails to disclose the required clock generator in order to generate the first, second, third, and fourth sets of quadrature phase carrier signals such that the required sets are in phase with one another. Rather Teng achieves this through varying the amplitude of the carrier signals in the I and Q path).
Patel teaches Patel makes no recitation of any clock generator, and the only recitations corresponding to clock frequencies or transmit time have no relevance to the first, second, third, and fourth quadrature phase carrier signals being in phase with one another, as required by the claim)
No other prior art teaches the required limitations either wholly or in part with sufficient motivation to combine.
Regarding claim 8, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 6. Teng, as modified in view of Patel fails to teach whereby a size of each transducer in each I-driver transducer pair is dependent on a gain of the I-driver.
Teng teaches whereby a size of each transducer in each I-driver transducer pair Teng makes no recitation of the size of each transducer in each I-driver transducer pair being dependent upon a gain of the I driver, as Teng at [pg. 1] states that the time division multiplexing is applied for the RX AFE so that a variable gain amplifier is used for each N-column pixel No other identified prior art discloses the size of the I-driver being selected based on the gain of the I-driver).
Regarding claim 9, Teng, as modified in view of Patel teaches he hardware accelerator according to claim 7. Teng, as modified in view of Patel fails to teach whereby a size of each transducer in each Q-driver transducer pair is dependent on a gain of the Q-driver.
Teng teaches whereby a size of each transducer in each Q-driver transducer pair Teng makes no recitation of the size of each transducer in each Q-driver transducer pair being dependent upon a gain of the Q-driver, as Teng at [pg. 1] states that the time division multiplexing is applied for the RX AFE so that a variable gain amplifier is used for each N-column pixel. No other identified prior art discloses the size of the Q-driver being selected based on the gain of the Q-driver).
Regarding claim 10, Teng, as modified in view of Patel teaches the hardware accelerator according to claim 1, Teng, as modified in view of Patel fails to teach whereby each IQ demodulator comprises: a transducer to receive ultrasonic waves from the lens and to convert the ultrasonic waves to received signals; a first double-balanced mixer configured to down convert the received signals from the transducer to differential I baseband signals using the third set of quadrature phase carrier signals; a second double-balanced mixer configured to down convert the received signals from the transducer to differential Q baseband signals using the fourth set of quadrature phase carrier signals; a differential multiplexer configured to combine the differential I and Q baseband signals and to provide the combined differential I and Q baseband signals to a low pass filter that is configured to provide the filtered signals to the plurality of analog baseband and ADC pairs.
Teng teaches whereby each IQ demodulator comprises: a transducer to receive ultrasonic waves from the lens and to convert the ultrasonic waves to received signals(fig. 1 (AIN transducer)([pg. 1] on-chip transmitter and receiver includes N x N transducers array) (Fig. 1 (lens);
a Teng makes no recitation of any double-balanced mixers, let alone two double-balanced mixers to down convert the received signals. Further, the multiplexing of Teng does not include the passing of combined differential I and Q baseband signals to a low pass filter. No other identified prior art teaches these limitations either wholly or in part with sufficient motivation to combine).
Regarding claim 11, the claims is indicated as containing allowable subject matter due to its respective dependency upon a claim indicated as containing allowable subject matter.
Regarding claim 12, the claim is indicated as containing allowable subject due to its respective dependence upon a claim containing allowable subject matter.
Regarding claim 15, the claim is a method claim corresponding to claim 2 and is therefore indicated as containing allowable subject matter for the same reasons.
Regarding claim 16, the claim is a method claim corresponding to claim 3 and is therefore indicated as containing allowable subject matter for the same reasons.
Regarding claim 19, the claim is a method claim corresponding to claim 10 and is therefore indicated as containing allowable subject matter for the same reasons.
Conclusion
Prior art made of record though not relied upon in the present basis of rejection are noted in the attached PTO 892 and include:
Woodruff et al. ("Bind the gap: Compiling real software to hardware FFT accelerators." Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation. 2022., “Jackson”) which discloses FFT hardware accelerators and associated software
Hwang et al. ("Planar GHz ultrasonic lens for fourier ultrasonics." 2019 IEEE International Ultrasonics Symposium (IUS). IEEE, 2019., “Hwang”) discloses an system and planar lens for Fourier ultrasonics
LAL (US 20210255032 A1, “LAL”) which discloses an ultrasonic Fourier Transform Analog Computing apparatus, method, and its associated applications
Abdelmejeed et al. "Towards digitally controlled ultrasonic IQ modulator." 2019 IEEE International Ultrasonics Symposium (IUS). IEEE, 2019., “Abdelmejeed”) which discloses techniques and apparatuses for digitally controlling an ultrasonic IQ modulator
Gal et al. ("Reconfigurable accelerator design platform for ultrasonic signal processing and imaging applications." 2016 IEEE international ultrasonics symposium (IUS). IEEE, 2016., “Gal”) which discloses various design considerations and platforms for reconfigurable ultrasonic hardware accelerators
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/CHRISTOPHER RICHARD WALKER/ Examiner, Art Unit 3645
/YUQING XIAO/ Supervisory Patent Examiner, Art Unit 3645
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