DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 12-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Toda (US 10,903,257 B2).
Regarding Claim 1, Toda teaches a photodetector ([Col. 6, ll. 40-45] (55) A solid-state imaging device 1 according to this embodiment includes a pixel region 3 including a plurality of pixels 2 arranged on a substrate 11 formed of silicon, a vertical driving circuit 4, column signal processing circuits 5, a horizontal driving circuit 6, an output circuit 7, and a control circuit 8), comprising:
a pixel array, wherein the pixel array includes a plurality of unit pixels, and wherein, in a plan view, the unit pixels are disposed in a plurality of rows and a plurality of columns ([Col. 6, ll. 53-54] The pixel region 3 includes the plurality of pixels 2 arranged regularly in the two-dimensional array Examiner Note: Fig. 1, reproduced below, shows the plurality of pixels disposed in a plurality of rows and a plurality of columns);
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a semiconductor substrate ([Col. 6, ll. 41-42] including a plurality of pixels 2 arranged on a substrate 11 formed of silicon);
a pixel isolation section, wherein the pixel isolation section is disposed in the semiconductor substrate ([Col. 7, l. 65] – [Col. 8, l. 2] The pixel isolation unit 20 is formed of a high-concentration p-type semiconductor layer formed at a desired depth from the back surface side of the substrate 12, and is provided for electrically isolating between the two adjacent pixels 2), wherein the pixel isolation section surrounds the unit pixels in the plan view (Fig. 2 Examiner Note: Fig. 2, reproduced below, is a plan view of the solid-state imaging device, and the light shielding film 22 is located above the pixel isolation section 20. The gaps in the light shielding film are aligned with the center of the lenses and are also aligned with the pixels in the array. On both sides of the pixels (aka surrounding them) are pixel isolation units (element 20)), and
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wherein a first unit pixel in the plurality of unit pixels includes:
a light receiving section ([Col. 7, ll. 60-64] the pixel region 3 having an impurity region that forms the pixel 2 such as the photoelectric conversion unit 17 is a well region 13 of a second conductivity type (p type in this embodiment)), wherein the light receiving section is disposed within an area formed by the pixel isolation section surrounding the first unit pixel in the plan view (Fig. 2 Examiner Note: Fig. 2, reproduced above, illustrates that the light receiving region 17 is disposed within an area formed by the pixel isolation sections 20), and wherein the light receiving section is disposed in the semiconductor substrate (Fig. 2 and [Col. 7, ll. 57-58] The substrate 12 is a semiconductor substrate formed of silicon Examiner Note: Fig. 2, reproduced above, shows that the light receiving region 17 is disposed in the semiconductor substrate 12);
a first electrode ([Col. 9, ll. 61-64] The first transfer gate electrode 27 included in the first transfer transistor Tr1 is a vertical gate electrode formed in the depth direction from the front surface side of the substrate 12), wherein the first electrode is disposed within the area formed by the pixel isolation section surrounding the first unit pixel in the plan view (Fig. 2 Examiner Note: Fig. 2, reproduced above, shows vertical transfer gate electrode 27 (first electrode) of transistor Tr1 extending vertically into semiconductor substrate 12 within the lateral boundary defined by high-concentration p-type pixel isolation unit 20 (pixel isolation section). “Disposed within the area formed by the pixel isolation section surrounding the first unit pixel in the plan view” has been interpreted to encompass any conductive element positioned inside the outer perimeter walls defined by the isolation unit 20); and
a second electrode ([Col. 10, ll. 26-30] The second transfer gate electrode 32 included in the second transfer transistor Tr2 is formed on the front surface side of the substrate 12 between the source and the drain with the gate insulation film 28 formed of, for example, a silicon oxide film interposed therebetween), wherein the second electrode is disposed within an area of the light receiving section of the first unit pixel in the plan view (Fig. 2 Examiner Note: Fig. 2, reproduced above, shows second transfer gate electrode 32 (second electrode) of transistor Tr2 disposed on the front surface of semiconductor substrate 12 directly adjacent to photoelectric conversion unit 17 (light receiving section). The “area of the light receiving section… in the plan view” has been interpreted to include the lateral substrate area occupied by, or immediately overlapping/interfaced with, photoelectric conversion unit 17 to enable charge transfer), and wherein the first electrode and the second electrode are disposed along a line that is oblique relative to the rows and columns of the pixel array (MPEP 2144.04 Examiner Note: Toda explicitly teaches integrating vertical gate electrode 27 (first electrode) and transfer gate electrode 32 (second electrode) within a unit pixel bounded by isolation section 20. Although Toda does not explicitly illustrate these specific spatial coordinates or diagonal alignment in a plan view, a person of ordinary skill in the art would recognize that modifying the relative location, placement, or geometric alignment of known function components, like rearranging electrodes along an oblique line relative to an orthogonal grid, is a routine rearrangement of parts and design optimization).
A person of ordinary skill in the art would before the effective filing date of the claimed invention would have been motivated to arrange the first electrode and second electrode along an oblique axis relative to the array grid in order to optimize surface real estate on the semiconductor substrate, shorten interconnect routing pathways, minimize parasitic line-to-line capacitance between adjacent gate conductors, and suppress crosstalk between adjacent unit pixels, yielding predictable results with no unexpected technical effect.
Regarding Claim 3, Toda teaches that a third electrode ([Col. 10, ll. 37-39] The first reset transistor Tr3 includes the floating diffusion unit 34 serving as a source, a drain 35 connected to a power source voltage Vdd, and a first reset gate electrode 33) is disposed along the line that is oblique relative to the rows and columns of the pixel array along which the first electrode and the second electrode are also disposed (MPEP 2144.04 Examiner Note: Disposing the third electrode on the oblique line of the first and second electrodes is a matter of routine spatial positioning and design choice), and wherein the first electrode is disposed between the second electrode and the third electrode (MPEP 2144.04 Examiner Note: Ordering the relative layout position of the electrodes along the shared axis is a routine rearrangement of parts).
Regarding the spatial placement and alignment of the third electrode along the oblique line, as well as placing the first electrode between the second and third electrode, Toda explicitly teaches integrating vertical gate electrode 27 (first electrode), transfer gate electrode 32 (second electrode), and reset gate electrode 33 (third electrode) within the unit pixel layout. To the extent that Doda does not explicitly illustrate this precise collinear oblique alignment or sequential ordering in plan view, a person of ordinary skill in the art would recognize that modifying the relative location, placement, or geometric alignment of known functional components, like arranging a first electrode between a second and third electrode along a shared diagonal axis, constitutes a routine rearrangement of parts and design optimization. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to arrange the third electrode collinearly along the oblique axis with the first and second electrodes and with the first electrode disposed between the second and third. They would have been motivated to do so to create a linear charge-transfer pathway from the light receiving section through the transfer gate to the floating diffusion/reset node, thereby minimizing interconnect path length, reducing parasitic line capacitance, and maximizing pixel surface layout efficiency, yielding predictable operational results with no unexpected technical effect.
Regarding Claim 4, Toda teaches that a distance between the first electrode and the second electrode is equal to a distance between the first electrode and the third electrode (MPEP 2144.04 Examiner Note: Configuring equal spacing between adjacent electrodes is a matter of routine dimensioning and design choice).
Regarding the relative spacing between the electrodes, Toda explicitly teaches integrating vertical gate electrode 27 (first electrode), transfer gate electrode 32 (second electrode), and reset gate electrode 33 (third electrode) within the unit pixel layout. To the extent that Toda does not explicitly recite equal physical distances between these electrode structures, a person of ordinary skill in the art would recognize that modifying the relative dimensions, spacing, or pitch between known functional components constitutes a routine rearrangement of parts and design optimization. A person of ordinary skill in the art before the filing date of the claimed invention would have been motivated to space the first, second, and third electrodes equidistantly in order to maintain uniform electric field distributions across the transfer channels, balance parasitic gate capacitance, equalize charge transfer timing, and optimize spatial pitch across the pixel substrate, yielding predictable operational results with no unexpected technical effect.
Regarding Claim 5, Toda teaches that the pixel isolation section extends between a first surface and a second surface of the semiconductor substrate (Fig. 2 Examiner Note: Fig. 2, reproduced above, illustrates that pixel isolation unit 20 is formed at a desired depth from the back surface side of the substrate 12, thereby extending between a first surface (the back surface of substrate 12) and a second surface (the inner boundary surface/depth boundary of the isolation region within substrate 12)).
Regarding Claim 6, Toda teaches that an electrode isolation section is disposed between the first electrode and the second electrode ([Col. 9, l. 67]-[Col. 10, l. 4] This first transfer gate electrode 27 is formed by embedding the electrode material into a trench formed at a desired depth from the front surface side of the substrate 12 with a gate insulation film 28 interposed therebetween).
Regarding Claim 12, Toda teaches that the pixel isolation section is connected to the electrode isolation section (Fig. 2 Examiner Note: Fig. 2, reproduced above, clearly shows that the pixel isolation section 20 and the electrode isolation section 28 are physically connected by the p-type well region 13).
Regarding Claim 13, Toda teaches that a light-shielding film is disposed on the first electrode (Fig. 2 Examiner Note: Fig. 2, reproduced above, shows that a light-shielding film 22 is disposed above the first electrode. Under the broadest reasonable interpretation, “disposed on” encompasses a layer formed above or overlaying a referenced element within a semiconductor substrate stack).
Regarding Claim 19, Toda teaches that the pixel isolation section extends between a first surface and a second surface of the semiconductor substrate (Fig. 2 Examiner Note: Fig. 2, reproduced above, shows high-concentration p-type pixel isolation unit 20 extending through semiconductor substrate 12 from the front surface side to the back surface side), and wherein the electrode isolation section extends from the first surface of the semiconductor substrate to a first depth within the semiconductor substrate (Fig. 2 Examiner Note: Fig. 2 shows gate insulating film 28 extending from the front surface to a partial depth within substrate 12 surrounding vertical gate electrode 37. MPEP 2144.04 Examiner Note: Although the specific depth profile is not explicitly recited, configuring the relative penetration depth and vertical extent of isolation features within the substrate is a matter of routine dimensioning and design choice).
Regarding the depth profile and extension of the electrode isolation section relative to the pixel isolation section, Toda explicitly teaches high-concentration p-type pixel isolation unit 20 extending through substrate 12 and gate insulating film 28 (electrode isolation section) extending into substrate 12 from the front surface (Fig. 2). Although Toda does not explicitly recite the exact penetration depth profile of the electrode isolation section, a person of ordinary skill in the art would recognize that modifying the relative depth, thickness, or vertical extent of functional isolation layers constitutes a routine rearrangement of parts and relative dimensioning. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to configure gate insulating film 28 to extend from the front surface to a targeted first depth within substrate 12. They would have been motivated to do so to ensure sufficient dielectric isolation around vertical transfer gate electrode 27, prevent leakage currents into adjacent semiconductor regions, and optimize electrostatic channel control within the substrate, yielding predictable results with no unexpected technical effect.
Claims 2 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Toda (US 10,903,257 B2), as applied to Claims 1, 3-6, 12-13, and 19 above, in view of Park et al. (US 2024/0022800 A1).
Regarding Claims 2 and 18, Toda is not relied upon as teaching that the light receiving section has an octagonal shape.
However, Park teaches that the light receiving section has an octagonal shape ([0075] The pixel PX may include a large photodiode LPD and a small photodiode SPD. A region where the large photodiode LPD is formed and a region where the small photodiode SPD is formed may be separated from each other by an isolation region such as a deep trench isolation (DTI) structure… the large photodiode LPD may have an octagonal shape such as a regular octagonal shape).
Toda and Park are considered to be analogous to the claimed invention because they are both in the same field of semiconductor photodetectors and pixel arrays. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the light receiving section of Toda to be the octagonal shape of Park with a reasonable expectation of success. This modification would have been motivated by the desire to maximize the active light-receiving surface area of the photodiode while reducing layout corners to prevent localized electronic field concentration and improve charge collection efficiency. By integrating Park’s teaching of an octagonal photodiode region into Toda’s pixel layout, the system can capture light more efficiently across the pixel layout without increasing unit pixel pitch. A person of ordinary skill in the art would recognize that shaping the photodiode as an octagon would yield the predictable result of optimizing light conversion area and improving photo-carrier generation within the pixel boundary.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Toda (US 10,903,257 B2), as applied to Claims 1, 3-6, 12-13, and 19, in view of Kokubun et al. (US 2020/0284923 A1).
Regarding Claim 7, Toda teaches that the electrode isolation section includes an insulating film ([Col. 9, l. 67]-[Col. 10, l. 4] This first transfer gate electrode 27 is formed by embedding the electrode material into a trench formed at a desired depth from the front surface side of the substrate 12 with a gate insulation film 28 interposed therebetween).
Toda is not relied upon as teaching that the pixel isolation section includes an insulating film.
However, Kokubun teaches that the pixel isolation section includes an insulating film ([0025] The pixel isolation film 13 is provided between the pixels 21. The pixel isolation film 13 isolates the pixels 21 from each other to prevent the occurrence of crosstalk between the pixels 21. For example, a silicon oxide film is used as the pixel isolation film 13).
Toda and Kokubun are considered to be analogous to the claimed invention because they are both in the same field of solid-state photodetectors and semiconductor pixel isolation structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pixel isolation section of Toda to include the insulating film of Kokubun with a reasonable expectation of success. This modification would have been motivated by the desire to prevent optical and electrical crosstalk between adjacent pixels. By integrating Kokubun’s teaching of a pixel isolation insulating film into Toda’s photodetector, the system can provide reliable dielectric isolation across both the pixel isolation section and the electrode isolation section. A person of ordinary skill in the art would recognize that utilizing an insulating film for pixel isolation in Toda’s device would yield the predictable result of reduced inter-pixel crosstalk and improved signal isolation.
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Toda (US 10,903,257 B2), as applied to Claims 1, 3-6, 12-13, and 19, in view of Van Der Tempel et al. (US 2019/0025414 A1).
Regarding Claim 8, Toda is not relied upon as teaching that the pixel isolation section and the electrode isolation section include an optical reflection film disposed between insulating films.
However, Van Der Tempel teaches that the pixel isolation section and the electrode isolation section include an optical reflection film disposed between insulating films ([0042] the isolation trench 103, can be for example a deep etch, with an isolator 1001 between the silicon surface of the etch. This can be for example, but not limited to, a silicium-oxide, and for example (but not limited to) a polysilicon plug 1002 in the etched trench).
Toda and Van Der Tempel are considered to be analogous to the claimed invention because they are both in the same field of photodetectors and image sensor isolation. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the isolation structure of Toda to include the oxide-lined trench structure containing an internal fill of Van Der Tempel with a reasonable expectation of success. This modification would have been motivated by the desire to prevent optical cross-talk between adjacent pixel regions. By integrating Van Der Tempel’s teaching of an oxide-lined trench structure into Toda’s isolation regions, the system can reflect incident light back into the active pixel cavity. A person of ordinary skill in the art would recognize that combining these features would yield the predictable result of improved optical isolation and light retention within individual pixels.
Regarding Claim 9, Toda is not relied upon as teaching that the optical reflection film includes an electrically conductive material.
However, Van Der Tempel teaches that the optical reflection film includes an electrically conductive material ([0042] a polysilicon plug 1002 in the etched trench… be filled with an electrical conductive material or semiconductor such that a voltage can be applied).
Toda and Van Der Tempel are considered to be analogous to the claimed invention because they are both in the same field of photodetectors and image sensor isolation. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the isolation trench fill material of Toda to include the electrically conductive material of Van Der Tempel with a reasonable expectation of success. This modification would have been motivated by the desire to enable electrical bias control across the trench while maintaining optical reflection. By integrating Van Der Tempel’s teaching of a conductive fill material (e.g., polysilicon or metal) into Toda’s isolation trench, the system can apply voltage potentials directly within the isolation barrier. A person of ordinary skill in the art would recognize that substituting conductive trench fill would yield the predictable result of integrated electro-optical pixel isolation.
Regarding Claim 10, Toda is not relied upon as teaching that optical reflection film is electrically connected to the first electrode.
However, Van Der Tempel teaches that optical reflection film is electrically connected to the first electrode ([0042] allows to bias the potential of the polysilicon plug to avoid channel formation on the etch surface, as illustrated in FIG. 4. The isolation means 103 are preferably biased with a potential Examiner Note: It would have been obvious to a person of ordinary skill in the art to tie the conductive trench plug directly or indirectly to the existing first electrode node/drive circuit of Toda to supply this bias potential).
Toda and Van Der Tempel are considered to be analogous to the claimed invention because they are both in the same field of photodetectors and image sensor isolation. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bias circuitry of Toda to include the electrically biased trench fill connection of Ven Der Tempel with a reasonable expectation of success. This modification would have been motivated by the desire to conveniently supply an operating bias voltage to the trench without routing dedicated secondary power lines. By integrating Van Der Tempel’s teaching of biasing the conductive trench plug into Toda’s electrode node, the system can distribute potential to the trench through existing pixel driver lines. A person of ordinary skill in the art would recognize that connecting the conductive trench fill to the electrode supply node would yield the predictable result of controlled interface potential via standard pixel wiring.
Regarding Claim 11, Toda is not relied upon as teaching that electrical potential applied to the optical reflection film is between an electrical potential applied to the first electrode and an electrical potential applied to the second electrode.
However, Van Der Tempel teaches that electrical potential applied to the optical reflection film is between an electrical potential applied to the first electrode and an electrical potential applied to the second electrode ([0042] allows to bias the potential of the polysilicon plug to avoid channel formation on the etch surface).
Toda and Van Der Tempel are considered to be analogous to the claimed invention because they are both in the same field of photodetectors and image sensor isolation. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the trench bias potential of Toda to include the intermediate voltage level of Van Der Tempel with a reasonable expectation of success. This modification would have been motivated by the desire to suppress interface generated dark current and prevent surface channel formation along etched silicon sidewalls. By integrating Van Der Tempel’s teaching of applying a potential to the conductive trench plug into Toda’s trench isolation, the system can passivate the silicon interface between operating electrode potential extremes. A person of ordinary skill in the art would recognize that tuning the trench bias to an intermediate potential would yield the predictable result of reduce surface state leakage and eliminated parasitic conduction channels.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Toda (US 10,903,257 B2), as applied to Claims 1, 3-6, 12-13, and 19, in view of Kanou et al. (US 2025/0337800 A1).
Regarding Claim 14, Toda is not relied upon as teaching a multiplication region, wherein the multiplication region includes a first semiconductor region having a first electrical conduction type and a second semiconductor region having a second electrical conduction type, and wherein the multiplication region is disposed within an area of the light receiving section of the first unit pixel.
However, Kanou teaches a multiplication region, wherein the multiplication region includes a first semiconductor region having a first electrical conduction type ([0067] The photoelectric conversion element 102 further includes a P-type second semiconductor region 312) and a second semiconductor region having a second electrical conduction type ([0067] The photoelectric conversion element 102 includes an N-type first semiconductor region 311), and wherein the multiplication region is disposed within an area of the light receiving section of the first unit pixel ([0069] When light incident on the photoelectric conversion element 102 is photoelectrically converted, and avalanche multiplication occurs in the depletion layer region (i.e., avalanche multiplication region), the generated first conductive type electric charges are collected in the first semiconductor region 311).
Toda and Kanou are considered to be analogous to the claimed invention because they are both in the same field of solid-state image sensors and photodetector structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the light receiving section of Toda to include the multiplication region of Kanou with a reasonable expectation of success. This modification would have been motivated by the desire to enable avalanche multiplication within the pixel’s light receiving area, thereby enhancing internal signal gain and improving sensitivity under low-light operating conditions. By integrating Kanou’s teaching of a multiplication region within the photoelectric conversion area into Toda’s light receiving section, the system can internalize charge multiplication directly at the photodetector site prior to signal transfer. A person of ordinary skill in the art would recognize that this modification would yield the predictable result of increasing photodetector gain and signal to noise ratio without requiring additional external amplifier stages.
Regarding Claim 15, Toda is not relied upon as teaching a third semiconductor region having the first electrical conduction type, wherein the third semiconductor region is disposed on a side surface of the pixel isolation section adjacent to the light receiving section of the first unit pixel.
However, Kanou teaches a third semiconductor region having the first electrical conduction type ([0067] a P-type fifth semiconductor region 315), wherein the third semiconductor region is disposed on a side surface of the pixel isolation section adjacent to the light receiving section of the first unit pixel ([0074] a pixel isolation part 324 having a trench structure, and the P-type fifth semiconductor region 315 formed in the periphery thereof isolates one photoelectric conversion element 102 from another photoelectric conversion element 102).
Toda (as previously modified by Kanou) and Kanou are considered to be analogous to the claimed invention because they are both in the same field of solid-state image sensors and photodetector structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pixel isolation section of Toda (as previously modified by Kanou) to include the third semiconductor region having the first electrical conduction type disposed on a side surface of the pixel isolation section of Kanou with a reasonable expectation of success. This modification would have been motivated by the desire to suppress dark current generation along the etched sidewalls of the trench-type pixel isolation structure and enhance electrical charge confinement within the light receiving section. By integrating Kanou’s teaching of forming a P-type semiconductor region along the periphery of the trench isolation structure into Toda, the system can passivate surface defects at the isolation interface. A person of ordinary skill in the art would recognize that this modification would yield the predictable result of minimizing interfacial carrier combination and reducing pixel to pixel optical and electrical crosstalk.
Regarding Claim 16, Toda is not relied upon as teaching a fourth semiconductor region having the first electrical conduction type; and a fifth semiconductor region having the second electrical conduction type, wherein the fourth and fifth semiconductor regions are disposed on the side surface of the pixel isolation section adjacent to the multiplication region.
However, Kanou teaches a fourth semiconductor region having the first electrical conduction type ([0067] a P-type third semiconductor region 313); and
a fifth semiconductor region having the second electrical conduction type ([0067] an N-type seventh semiconductor region 317), wherein the fourth and fifth semiconductor regions are disposed on the side surface of the pixel isolation section adjacent to the multiplication region ([0068] the N-type seventh semiconductor region 317 is formed in a periphery of the first semiconductor region 311 [0071] A concavo-convex structure 325 configured of trench portions is formed on a surface of a semiconductor layer 301 on a side of a light incident plane. The concavo-convex structure 325 is surrounded by the P-type third semiconductor region 313 [0074] One pixel 101 is isolated from another pixel 101 by a pixel isolation part 324 having a trench structure, and the P-type fifth semiconductor region 315 formed in the periphery thereof isolates one photoelectric conversion element 102 from another photoelectric conversion element 102 adjacent thereto with a potential barrier).
Toda (as previously modified by Kanou) and Kanou are considered to be analogous to the claimed invention because they are both in the same field of solid-state image sensors and photodetector structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pixel isolation section of Toda to include the fourth semiconductor region having the first electrical conduction type and the fifth semiconductor region having the second electrical conduction type disposed on the side surface of the pixel isolation section adjacent to the multiplication region of Kanou with a reasonable expectation of success. This modification would have been motivated by the desire to establish proper potential profiles and electrical isolation boundaries surrounding the avalanche multiplication region, preventing uncollected carriers from overflowing while passivating etched sidewall interfaces. By integrating Kanou’s teaching of disposing p-type and n-type semiconductor regions along the periphery of the isolation trench adjacent to the multiplication region into Toda, the system can precisely channel impact-ionized charge carriers and control electric field distribution within the multiplication zone. A person of ordinary skill in the art would recognize that this modification would yield the predictable result of optimizing avalanche multiplication efficiency while preventing inter-pixel crosstalk and parasitic leakage currents.
Regarding Claim 17, Toda is not relied upon as teaching that the fifth semiconductor region is connected to the second electrode.
However, Kanou teaches that the fifth semiconductor region is connected to the second electrode (Fig. 6 Examiner Note: Fig. 6, reproduced below, shows that the fifth semiconductor region 317 is physically and electrically connected to electrode contact 219 via contiguous semiconductor regions 312 and 315. Because regions 317, 312, 315, and electrode contact 319 form a continuous physical and conductive pathway, Kanou satisfies the requirement that the fifth semiconductor region is connected to the second electrode)
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Toda (as previously modified by Kanou) and Kanou are considered to be analogous to the claimed invention because they are both in the same field of solid-state image sensors and photodetector structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Toda to connect the fifth semiconductor region to the second electrode as taught by Kanou with a reasonable expectation of success. This modification would have been motivated by the desire to establish a direct bias/charge collection pathway to the fifth semiconductor region. By integrating Kanou’s teaching of connecting the fifth semiconductor region to the electrode, the system can efficiently route accumulated carriers from the isolation region. A person of ordinary skill in the art would recognize that this modification would yield the predictable result of facilitating signal readout and preventing charge accumulation.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Toda (US 10,903,257 B2) in view of Zhou et al. (US 12,571,888 B2).
Regarding Claim 20, Toda teaches a photodetector ([Col. 6, ll. 40-45] (55) A solid-state imaging device 1 according to this embodiment includes a pixel region 3 including a plurality of pixels 2 arranged on a substrate 11 formed of silicon, a vertical driving circuit 4, column signal processing circuits 5, a horizontal driving circuit 6, an output circuit 7, and a control circuit 8), including:
a pixel array, wherein the pixel array includes a plurality of unit pixels, wherein, in a plan view, the unit pixels are disposed in a plurality of rows and a plurality of columns ([Col. 6, ll. 53-54] The pixel region 3 includes the plurality of pixels 2 arranged regularly in the two-dimensional array Examiner Note: Fig. 1, reproduced above, shows the plurality of pixels disposed in a plurality of rows and a plurality of columns);
a semiconductor substrate ([Col. 6, ll. 41-42] including a plurality of pixels 2 arranged on a substrate 11 formed of silicon);
a pixel isolation section, wherein the pixel isolation section is disposed in the semiconductor substrate ([Col. 7, l. 65] – [Col. 8, l. 2] The pixel isolation unit 20 is formed of a high-concentration p-type semiconductor layer formed at a desired depth from the back surface side of the substrate 12, and is provided for electrically isolating between the two adjacent pixels 2), wherein the pixel isolation section surrounds the unit pixels in a plan view (Fig. 2 Examiner Note: Fig. 2, reproduced above, is a plan view of the solid-state imaging device, and the light shielding film 22 is located above the pixel isolation section 20. The gaps in the light shielding film are aligned with the center of the lenses and are also aligned with the pixels in the array. On both sides of the pixels (aka surrounding them) are pixel isolation units (element 20)), and wherein a first unit pixel in the plurality of unit pixels includes:
a light receiving section ([Col. 7, ll. 60-64] the pixel region 3 having an impurity region that forms the pixel 2 such as the photoelectric conversion unit 17 is a well region 13 of a second conductivity type (p type in this embodiment)), wherein the light receiving section is disposed within an area formed by the pixel isolation section surrounding the first unit pixel in the plan view (MPEP 2144.04 Fig. 2 Examiner Note: Fig. 2, reproduced above, illustrates that the light receiving region 17 is disposed within an area formed by the pixel isolation sections 20, ensuring that the light receiving regions are surrounded by the pixel isolation sections in a plan view is a matter of routine design optimization and rearrangement of parts ), and wherein the light receiving section is disposed in the semiconductor substrate (Fig. 2 and [Col. 7, ll. 57-58] The substrate 12 is a semiconductor substrate formed of silicon Examiner Note: Fig. 2, reproduced above, shows that the light receiving region 17 is disposed in the semiconductor substrate 12);
a first electrode ([Col. 9, ll. 61-64] The first transfer gate electrode 27 included in the first transfer transistor Tr1 is a vertical gate electrode formed in the depth direction from the front surface side of the substrate 12), wherein the first electrode is disposed within the area formed by the pixel isolation section surrounding the first unit pixel in the plan view (Fig. 2 Examiner Note: Fig. 2, reproduced above, shows vertical transfer gate electrode 27 (first electrode) of transistor Tr1 extending vertically into semiconductor substrate 12 within the lateral boundary defined by high-concentration p-type pixel isolation unit 20 (pixel isolation section). “Disposed within the area formed by the pixel isolation section surrounding the first unit pixel in the plan view” has been interpreted to encompass any conductive element positioned inside the outer perimeter walls defined by the isolation unit 20); and
a second electrode ([Col. 10, ll. 26-30] The second transfer gate electrode 32 included in the second transfer transistor Tr2 is formed on the front surface side of the substrate 12 between the source and the drain with the gate insulation film 28 formed of, for example, a silicon oxide film interposed therebetween), wherein the second electrode is disposed within an area of the light receiving section of the first unit pixel in the plan view (Fig. 2 Examiner Note: Fig. 2, reproduced above, shows second transfer gate electrode 32 (second electrode) of transistor Tr2 disposed on the front surface of semiconductor substrate 12 directly adjacent to photoelectric conversion unit 17 (light receiving section). The “area of the light receiving section… in the plan view” has been interpreted to include the lateral substrate area occupied by, or immediately overlapping/interfaced with, photoelectric conversion unit 17 to enable charge transfer), and wherein the first electrode and the second electrode are disposed along a line that is oblique relative to the rows and columns of the pixel array (MPEP 2144.04 Examiner Note: Toda explicitly teaches integrating vertical gate electrode 27 (first electrode) and transfer gate electrode 32 (second electrode) within a unit pixel bounded by isolation section 20. Although Toda does not explicitly illustrate these specific spatial coordinates or diagonal alignment in a plan view, a person of ordinary skill in the art would recognize that modifying the relative location, placement, or geometric alignment of known function components, like rearranging electrodes along an oblique line relative to an orthogonal grid, is a routine rearrangement of parts and design optimization).
A person of ordinary skill in the art would before the effective filing date of the claimed invention would have been motivated to arrange the first electrode and second electrode along an oblique axis relative to the array grid in order to optimize surface real estate on the semiconductor substrate, shorten interconnect routing pathways, minimize parasitic line-to-line capacitance between adjacent gate conductors, and suppress crosstalk between adjacent unit pixels, yielding predictable results with no unexpected technical effect.
Toda is not relied upon as teaching a distance measurement apparatus, comprising: a light source device, wherein the light source device is operable to project light; an optical system, wherein the optical system is operable to collect light projected from the light source device and reflected from a target; a pixel array wherein the optical system guides the collected light to the pixel array; and an image processing circuit, wherein the image processing circuit is operable to construct a distance image based on a distance signal supplied from the photodetector.
However, Zhou teaches a distance measurement apparatus ([Col. 11, l. 22] LiDAR system), comprising:
a light source device, wherein the light source device is operable to project light ([Col. 10, ll. 3-10] Light signal generator 1030 may include circuitry (e.g., a laser diode) configured to generate a light signal, which can be used as the LiDAR send signal, according to certain embodiments. In some cases, light signal generator 1030 may generate a laser that is used to generate a continuous or pulsed laser beam at any suitable electromagnetic wavelengths spanning the visible light spectrum and non-visible light spectrum (e.g., ultraviolet and infra-red));
an optical system, wherein the optical system is operable to collect light projected from the light source device and reflected from a target (Col. 1, ll. 25-29] For example, a LiDAR system may transmit a light beam (e.g., a pulsed laser beam) to illuminate a target and then measure the time it takes for the transmitted light beam to arrive at the target and then return to a receiver near the transmitter or at a known location.);
a pixel array ([Col. 11, ll. 30-35] Detector (s) 1060 can use any suitable photodetector technology including solid state photodetectors (e.g., silicon avalanche photodiodes, complimentary metal-oxide semiconductors (CMOS), charge-coupled devices (CCD), hybrid CMOS/CCD devices) or photomultipliers) wherein the optical system guides the collected light to the pixel array ([Col. 1, ll. 59-63] Returning pulses are photons that, depending on the return angle, will hit different ones of the photodiodes in the array. The photons from different angles are focused by a lens system to different pixels (photodiodes) in the photodiode array); and
an image processing circuit, wherein the image processing circuit is operable to construct a distance image based on a distance signal supplied from the photodetector ([Col. 1, ll. 34-38] The data points in the point cloud may be dynamically and continuously updated, and may be used to estimate, for example, a distance, dimension, location, and speed of an object relative to the LiDAR system).
Toda and Zhou are considered analogous to the claimed invention because they are both in the same field of solid-state photodetectors and optical sensing devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the solid-state photodetector pixel array of Toda to include the optical distance measurement architecture and LiDAR system of Zhou with a reasonable expectation of success. This modification would have been motivated by the desire to integrate high-density, low-crosstalk photodetector arrays into optical depth sensing systems. By integrating Zhou’s teaching of distance measurement and LiDAR processing circuitry into Toda’s pixel array system, the system can collect reflected light pulses to accurately generate distance images and point cloud data. A person of ordinary skill in the art would recognize that combining Toda’s pixel structure with Zhou’s distance measurement apparatus would yield the predictable result of improved light collection efficiency and reduced inter-pixel interference during distance image construction.
Conclusion
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/E.H.H./Patent Examiner, Art Unit 3645
/JAMES R HULKA/Primary Examiner, Art Unit 3645
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